ATmega406 Atmel Corporation, ATmega406 Datasheet - Page 149

• Manufacturer Part Number: ATmega406
• Manufacturer: Atmel Corporation

Specifications of ATmega406

• Flash (kbytes): 40 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 1 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -30 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 2
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.6.4
25.6.5
2548E–AVR–07/06
TWDR – TWI Data Register
TWAR – TWI (Slave) Address Register
Table 25-2.
To calculate bit rates, see
in the equation.
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR
contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.
This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the data register
cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains sta-
ble as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted
in. TWDR always contains the last byte present on the bus, except after a wake-up from a sleep
mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost
bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is
controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
• Bits 7:0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received
on the Two-wire Serial Bus.
The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of
TWAR) to which the TWI will respond when programmed as a slave transmitter or Receiver, and
not needed in the Master modes. In multi-master systems, TWAR must be set in masters which
can be addressed as slaves by other masters.
The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an
associated address comparator that looks for the slave address (or general call address if
enabled) in the received serial address. If a match is found, an interrupt request is generated.
• Bits 7:1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit.
Bit
(0xBB)
Read/Write
Initial Value
Bit
(0xBA)
Read/Write
Initial Value
TWPS1
0
0
1
1
TWI Bit Rate Prescaler
TWD7
TWA6
R/W
R/W
7
1
7
1
TWD6
TWA5
R/W
R/W
”Bit Rate Generator Unit” on page
6
1
6
1
TWD5
TWA4
TWPS0
R/W
R/W
5
1
5
1
0
1
0
1
TWD4
TWA3
R/W
R/W
4
1
4
1
TWA2
TWD3
R/W
R/W
1
3
1
3
145. The value of TWPS1:0 is used
TWA1
TWD2
R/W
R/W
2
1
2
1
Prescaler Value
TWA0
TWD1
R/W
R/W
1
1
1
1
16
64
1
4
ATmega406
TWGCE
TWD0
R/W
R/W
0
1
0
0
TWDR
TWAR
149