ATmega406 Atmel Corporation, ATmega406 Datasheet - Page 127

• Manufacturer Part Number: ATmega406
• Manufacturer: Atmel Corporation

Specifications of ATmega406

• Flash (kbytes): 40 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 1 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -30 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 2
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22.5
22.6
2548E–AVR–07/06
Short-circuit Protection
Battery Protection CPU Interface
A second level of high current detection is provided to enable a faster response time to very
large discharge currents. If a discharge current larger than the Short-circuit Detection Level is
present for a period longer than Short-circuit Reaction Time, the Short-circuit Protection is
activated.
When the Short-circuit Protection is activated, the external D-FET, PC-FET, and C-FET are dis-
abled and a Current Protection Timer is started. This timer ensures that the D-FET, PC-FET,
and C-FET are disabled for at least one second. The application software must then set the DFE
and CFE bits in the FET Control and Status Register to re-enable normal operation. If the D-FET
is re-enabled before the cause of the short-circuit condition is removed, the Short-circuit Protec-
tion will be activated again.
The Over-current and Short-circuit Protection parameters are programmable to adapt to different
types of batteries. The parameters are set by writing to I/O Registers. The Parameter Registers
can be locked after the initial configuration, prohibiting any further updates until the next Hard-
ware Reset.
Refer to
The Battery Protection CPU Interface is illustrated in
Figure 22-1. Battery Protection CPU Interface
Each protection has an Interrupt Flag. Each Flag can be read and cleared by the CPU, and each
flag has an individual interrupt enable. All enabled flags are combined into a single battery pro-
tection interrupt request to the CPU. This interrupt can wake up the CPU from any operation
mode, except Power-off. The interrupt flags are cleared by writing a logic ‘1’ to their bit locations
from the CPU.
Note that there are neither flags nor status bits indicating that the chip has entered the Power Off
mode. This is because the CPU is powered down in this mode. The CPU will, however be able
Battery Protection
”Register Description for Battery Protection” on page 128
Parameter Lock
Register
VFET
PPI
NNI
Battery Protection
Level Register
LOCK?
Battery Protection
Timing Register
LOCK?
Protection
Protection
Current
Voltage
Battery
Battery
Battery Protection
Control Register
Deep Under-voltage
LOCK?
Figure
22-1.
Power-off
Interrupt
Request
for register descriptions.
Protection
Current
ATmega406
8-BIT DATA BUS
Acknowledge
Protection
Interrupt
Register
Interrupt
Battery
Control
8
/
FET
4
4
/
/
127