ATmega8 Atmel Corporation, ATmega8 Datasheet
ATmega8
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ATmega8 Summary of contents
Page 1
... PDIP, 32-lead TQFP, and 32-pad QFN/MLF • Operating Voltages – 2.7V - 5.5V (ATmega8L) – 4.5V - 5.5V (ATmega8) • Speed Grades – 8MHz (ATmega8L) – 16MHz (ATmega8) • Power Consumption at 4Mhz, 3V, 25°C – Active: 3.6mA – Idle Mode: 1.0mA – Power-down Mode: 0.5µA ® ® ...
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... Pin Configurations ATmega8(L) 2 PDIP (RESET) PC6 1 28 PC5 (ADC5/SCL) (RXD) PD0 2 27 PC4 (ADC4/SDA) (TXD) PD1 3 26 PC3 (ADC3) (INT0) PD2 4 25 PC2 (ADC2) (INT1) PD3 5 24 PC1 (ADC1) (XCK/T0) PD4 6 23 PC0 (ADC0) VCC 7 22 GND GND 8 21 AREF (XTAL1/TOSC1) PB6 ...
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... Overview The Atmel architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1MIPS per MHz, allowing the system designer to optimize power con- sumption versus processing speed. Block Diagram Figure 1. Block Diagram RESET VCC GND 2486Z–AVR–02/11 ® ...
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... RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega8 is supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evalu- ation kits. ...
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... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega8 as listed on 63. RESET Reset input ...
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... In the TQFP and QFN/MLF package, ADC7..6 serve as analog inputs to the A/D converter. QFN/MLF Package These pins are powered from the analog supply and serve as 10-bit ADC channels. Only) ATmega8( even if the ADC is not used. If the ADC is used, it should be con- CC through a low-pass filter. Note that Port C (5..4) use digital supply voltage ...
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... A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 2486Z–AVR–02/11 1. ATmega8(L) 7 ...
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... These code examples assume that the part specific header file is included before compi- Examples lation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling compiler dependent. Please confirm with the C compiler documentation for more details. ATmega8(L) 8 2486Z–AVR–02/11 ...
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... AVR core architecture in general. The main function of the Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega8(L) Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog Timer ALU ...
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... The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. ATmega8(L) 10 2486Z–AVR–02/11 ...
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... S R/W R/W R/W R/W R “Instruction Set Description” for detailed information. ⊕ V “Instruction Set Description” for detailed information. Description” for detailed information. Description” for detailed information. ATmega8(L) see “Instruction Set Summary” SREG R/W R/W R Instruction Set Reference ...
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... Data Space. Although not being physically imple- mented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-pointer, Y-pointer, and Z-pointer Registers can be set to index any register in the file. ATmega8(L) 12 shows the structure of the 32 general purpose working registers in the CPU. 7 ...
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... SP7 SP6 SP5 SP4 R/W R/W R/W R/W R/W R/W R/W R ® CPU is driven by the CPU clock clk ATmega8(L) Figure R26 (0x1A R28 (0x1C R30 (0x1E) Instruction Set Reference SP11 SP10 SP9 SP8 SP3 SP2 SP1 ...
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... Vector Select (IVSEL) bit in the General Interrupt Control Register (GICR). Refer to “Interrupts” on page 46 the boot Flash section by programming the BOOTRST Fuse, see While-Write Self-Programming” on page ATmega8(L) 14 shows the parallel instruction fetches and instruction executions enabled by the Har- T1 clk ...
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... SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ 2486Z–AVR–02/11 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ATmega8(L) 15 ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incre- mented by 2, and the I-bit in SREG is set. ATmega8( set global interrupt enable ® ...
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... Boot Program section and Application Program section. Memory The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega8 Pro- gram Counter (PC bits wide, thus addressing the 4K Program memory locations. The operation of Boot Program section and associated Boot Lock Bits for software protection are described in detail in 202 ...
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... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of internal data SRAM in the ATmega8 are all accessible through all these addressing modes. The Register File is described in Figure 8. Data Memory Map ...
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... SRAM access is performed in two clk Figure 9. On-chip Data SRAM Access Cycles EEPROM Data The ATmega8 contains 512bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at Memory least 100,000 write/erase cycles ...
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... Read/Write Initial Value • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega8 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the 512bytes EEPROM space ...
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... Table 1. EEPROM Programming Time Symbol EEPROM Write (from CPU) Note: 2486Z–AVR–02/11 Number of Calibrated RC Oscillator Cycles 1. Uses 1MHz clock, independent of CKSEL Fuse settings ATmega8(L) for details about boot Table 1 lists the typical pro- (1) Typ Programming Time 8448 8.5ms “Boot Loader ...
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... EEPROM_write(unsigned int uiAddress, unsigned char ucData Wait for completion of previous write */ while(EECR & (1<<EEWE)) /* Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } ATmega8( 2486Z–AVR–02/11 ...
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... Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; the EEPROM data can be corrupted because the supply voltage is CC, ATmega8(L) Reset Protec ...
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... The I/O and Peripherals Control Registers are explained in later sections. ATmega8(L) 24 ® ® AVR ATmega8 I/Os and peripherals are placed in the I/O space. The I/O locations for more details. When using the I/O specific commands IN and OUT, the I/O “Register Summary” on page 280. “Instruction Set Sum- 2486Z–AVR–02/11 ...
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... AVR Clock I/O Control Unit clk ASY Clock Multiplexer External RC Oscillator Oscillator External Clock is halted, enabling TWI address reception in all sleep modes. I/O ATmega8(L) ® ® AVR and their distribution. All of CPU Core RAM clk ADC clk CPU clk FLASH Reset Logic ...
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... The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in The frequency of the Watchdog Oscillator is voltage dependent as shown in “ATmega8 Typical Characteristics”. The device is shipped with CKSEL = “0001” and SUT = “10” (1MHz Internal RC Oscillator, slowly rising power) ...
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... This option should not be used with crystals, only with ceramic resonators 28. ATmega8(L) Figure 11. Either a quartz crystal or a Table 4. For ceramic resonators, the XTAL2 XTAL1 GND Table 4. Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – ...
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... Table 6. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection SUT1.. Note: External RC For timing insensitive applications, the external RC configuration shown in can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at Oscillator ATmega8(L) 28 Start-up Time from Power-down SUT1..0 and Power-save (1) 00 258 CK (1) 01 ...
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... Power-down and from Reset Power-save ( 4.1ms 18 CK 65ms ( 4.1ms 1. This option should not be used when operating close to the maximum frequency of the device ATmega8(L) NC XTAL2 XTAL1 GND Frequency Range (MHz) 0.1 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 12.0 = 5.0V) Recommended Usage – BOD enabled Fast rising power ...
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... PB6 (XTAL1/TOSC1) and PB7(XTAL2/TOSC2) can be used as either general I/O pins or Timer Oscillator pins.. Table 10. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection SUT1.. ( Note: ATmega8(L) 30 “Calibration Byte” on page CKSEL3..0 (1) 0001 0010 0011 0100 1. The device is shipped with this option selected ...
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... Table 11. Internal RC Oscillator Frequency Range OSCCAL Value 0xFF 2486Z–AVR–02/ CAL7 CAL6 CAL5 CAL4 R/W R/W R/W R/W Device Specific Calibration Value Min Frequency in Percentage of Nominal Frequency (%) 0x00 50 0x7F 75 100 ATmega8( CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W Table 11. Max Frequency in Percentage of Nominal Frequency (%) 100 150 200 OSCCAL 31 ...
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... By programming the CKOPT Fuse, the user can enable Oscillator internal capacitors on XTAL1 and XTAL2, thereby removing the need for external capacitors. The Oscillator is optimized for use with a 32.768kHz watch crystal. Applying an external clock source to TOSC1 is not recommended. Note: ATmega8(L) 32 EXTERNAL CLOCK SIGNAL Start-up Time from ...
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... Reset Vector. Note that the Extended Standby mode present in many other AVR MCUs has been removed in the ATmega8, as the TOSC and XTAL inputs share the same physical pins. Figure 10 on page 25 tion. The figure is helpful in selecting an appropriate sleep mode. ...
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... Power-save mode because the contents of the registers in the asynchronous timer should be considered undefined after wake-up in Power-save mode if AS2 is 0. This sleep mode basically halts all clocks except clk modules, including Timer/Counter 2 if clocked asynchronously. ATmega8(L) 34 and clk , while allowing the other clocks to run. ...
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... Analog Comparator. 2486Z–AVR–02/11 Oscillators Main Clock Timer Osc. clk clk Source Enabled Enabled ADC ASY ( “Analog Comparator” on page 186 ATmega8(L) Wake-up Sources TWI SPM/ INT1 Address Timer EEPROM INT0 Match 2 Ready ( (2) ( ...
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... In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to V ATmega8(L) 36 “Brown-out Detection” on page 40 for details on the start-up time. ...
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... CKSEL Fuses. The different selec- tions for the delay period are presented in Reset Sources The ATmega8 has four sources of Reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • ...
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... V antees that a Brown-out Reset will occur before V operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 for ATmega8L and BODLEVEL = 0 for ATmega8. BODLEVEL = 1 is not appli- cable for ATmega8 DATA BUS ...
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... Table 15 on page 38. The POR is activated whenever V rise. The RESET signal is activated again, without any delay, CC decreases below the detection level POT RST RESET t TOUT RESET V POT V CC RESET RESET ATmega8(L) is below the detection RST t TOUT 39 ...
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... MCU after the time-out period t Figure 17. External Reset During Operation Brown-out Detection ATmega8 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL pro- grammed) ...
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... Initial Value • Bit 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega8 and always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...
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... Internal Voltage ATmega8 features an internal bandgap reference. This reference is used for Brown-out Detec- Reference tion, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference. Voltage Reference The voltage reference has a start-up time that may influence the way it should be used. The ...
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... Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega8 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to 3 – ...
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... The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (for example, by disabling interrupts glob- ally) so that no interrupts will occur during execution of these functions. ATmega8(L) 44 Table 17. Number of WDT ...
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... Write logical one to WDCE and WDE r16, WDTCR in ori r16, (1<<WDCE)|(1<<WDE) out WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret /* reset WDT */ _WDR(); /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; ATmega8(L) 45 ...
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... Interrupts This section describes the specifics of the interrupt handling performed by the ATmega8. For a general explanation of the AVR interrupt handling, refer to page 14. Interrupt Vectors in ATmega8 Table 18. Reset and Interrupt Vectors Vector No Notes: Table 19 on page 47 of BOOTRST and IVSEL settings ...
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... Table 19. Reset and Interrupt Vectors Placement BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega8 is: addressLabels Code $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d ...
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... Reset and Interrupt Vector Addresses is: AddressLabels Code .org $001 $001 $002 ... $012 ; .org $c00 $c00 ; $c01 $c02 $c03 $c04 $c05 $c06 ATmega8(L) 48 rjmp RESET RESET:ldi r16,high(RAMEND); Main program start out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei ; Enable interrupts <instr> xxx rjmp EXT_INT0 ...
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... Enable interrupts <instr> xxx INT1 INT0 – – R/W R for details. To avoid unintentional changes of Interrupt Vector ATmega8( – – IVSEL IVCE GICR R R R/W R “Boot Loader Support – Read-While-Write “Boot Loader for details on Boot Lock Bits. ...
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... Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out GICR, r16 ; Move interrupts to boot Flash section ldi r16, (1<<IVSEL) out GICR, r16 ret C Code Example void Move_interrupts(void Enable change of Interrupt Vectors */ GICR = (1<<IVCE); /* Move interrupts to boot Flash section */ GICR = (1<<IVSEL); } ATmega8(L) 50 2486Z–AVR–02/11 ...
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... Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 2486Z–AVR–02/11 and Ground as indicated in CC for a complete list of parameters. Pxn C pin “Register Description for I/O Ports” on page ATmega8(L) Figure 21. Refer to “Electrical Charac Logic See Figure "General Digital I/O" for Details 65. “ ...
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... If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). ATmega8(L) 52 (1) PUD: ...
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... Input 0 X Output 1 X Output Figure 22 on page SYSTEM CLK XXX SYNC LATCH PINxn r17 ATmega8(L) Pull-up Comment No Tri-state (Hi-Z) Pxn will source current if external Yes pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) 52, the PINxn Register bit and the preceding ...
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... When reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in clock. In this case, the delay t Figure 24. Synchronization when Reading a Software Assigned Pin Value INSTRUCTIONS ATmega8(L) 54 and t pd,max pd,min Figure 24. The out instruction sets the “ ...
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... Figure 22 on page 52, the digital input signal can be clamped to ground at the input ATmega8(L) “Alternate Port Functions” on page / ...
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... The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 25. Alternate Port Functions Note: ATmega8( GND is not recommended, since this may cause excessive currents if the pin is CC ...
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... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. Analog Input/output This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally. ATmega8(L) Fig- 57 ...
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... Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin. If PB6 is used as a clock pin, DDB6, PORTB6 and PINB6 will all read 0. ATmega8( ...
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... MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. 2486Z–AVR–02/11 and Table 24 on page 60 relate the alternate functions of Port B to the Figure 25 on page 56. SPI MSTR INPUT and SPI SLAVE OUTPUT ATmega8(L) 59 ...
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... DIEOE DIEOV DI AIO Notes: Table 24. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega8(L) 60 PB7/XTAL2/ PB6/XTAL1/ (1)(2) (1) TOSC2 TOSC1 EXT • (INTRC + INTRC + AS2 AS2 EXT • (INTRC + INTRC + AS2 AS2 ...
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... RESET (Reset pin) ADC5 (ADC Input Channel 5) SCL (Two-wire Serial Bus Clock Line) ADC4 (ADC Input Channel 4) SDA (Two-wire Serial Bus Data Input/Output Line) ADC3 (ADC Input Channel 3) ADC2 (ADC Input Channel 2) ADC1 (ADC Input Channel 1) ADC0 (ADC Input Channel 0) ATmega8(L) Table 25. 61 ...
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... Table 27. Overriding Signals for Alternate Functions in PC3..PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: ATmega8(L) 62 and Table 27 relate the alternate functions of Port C to the overriding signals shown in 56. PC6/RESET PC5/SCL/ADC5 RSTDISBL TWEN 1 PORTC5 • PUD RSTDISBL ...
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... XCK (USART External Clock Input/Output) T0 (Timer/Counter 0 External Counter Input) INT1 (External Interrupt 1 Input) INT0 (External Interrupt 0 Input) TXD (USART Output Pin) RXD (USART Input Pin) and Table 30 on page 64 relate the alternate functions of Port D to the Figure 25 on page 56. ATmega8(L) Table 28. 63 ...
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... Signal Name PUOE PUO OOE OO PVOE PVO DIEOE DIEO DI AIO Table 30. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUO OOE OO PVOE PVO DIEOE DIEO DI AIO ATmega8(L) 64 PD7/AIN1 PD6/AIN0 PD5/ ...
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... R/W R/W R/W R DDD7 DDD6 DDD5 DDD4 R/W R/W R/W R PIND7 PIND6 PIND5 PIND4 N/A N/A N/A N/A ATmega8( PORTB3 PORTB2 PORTB1 PORTB0 R/W R/W R/W R DDB3 DDB2 DDB1 DDB0 R/W R/W R/W R PINB3 PINB2 PINB1 PINB0 ...
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... Table 31. Interrupt 1 Sense Control ISC11 ATmega8(L) 66 25. Low level interrupts on INT0/INT1 are detected “Electrical Characteristics” on page 25. If the level is sampled twice by the Watchdog Oscillator clock but ...
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... The rising edge of INT0 generates an interrupt request INT1 INT0 – – R/W R INTF1 INTF0 – – R/W R ATmega8( – – IVSEL IVCE GICR R R R/W R – – – – GIFR ...
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... SREG and the INT0 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. ATmega8(L) 68 2486Z–AVR–02/11 ...
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... TCNTn = 0xFF Table 33 are also used extensively throughout this datasheet. The counter reaches the BOTTOM when it becomes 0x00 The counter reaches its MAXimum when it becomes 0xFF (decimal 255) ATmega8(L) Figure 26. For the actual place- 2. CPU accessible I/O Registers, 71. TOVn (Int.Req.) Clock Select ...
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... The Timer/Counter is a synchronous design and the timer clock (clk Timing Diagrams clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. figure shows the count sequence close to the MAX value. ATmega8(L) 70 DATA BUS count TCNTn ...
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... Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O MAX - – – – – ATmega8(L) MAX BOTTOM /8) clk_I/O MAX BOTTOM – CS02 CS01 CS00 R R/W R/W R BOTTOM + 1 BOTTOM + 1 TCCR0 ...
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... The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard- ware when executing the corresponding interrupt Handling Vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. ATmega8(L) 72 CS01 CS00 ...
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... The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 /clk I/O Synchronization < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O ATmega8(L) /8, f /64, f CLK_I/O CLK_I/O pulse for each positive (CSn2 negative Edge Detector /256, or CLK_I/O Figure 30 ) ...
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... The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero. ATmega8(L) 74 Clear ...
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... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the 2486Z–AVR–02/11 “Pin Configurations” on page “16-bit Timer/Counter Register Description” on page ATmega8(L) Figure 32 on page 76. For the 2. CPU accessible I/O Regis- 96. ...
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... The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC1A/B). put Compare Units” on page 83. Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. ATmega8(L) 76 Count Clear ...
Page 77
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation. ATmega8(L) 77 ...
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... The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. ATmega8(L) 78 (1) (1) 1. See “ ...
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... Restore Global Interrupt Flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save Global Interrupt Flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into TCNT1; /* Restore Global Interrupt Flag */ SREG = sreg; return i; 1. See “About Code Examples” on page 8 ATmega8(L) 79 ...
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... Timer/Counter Control Register B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 33 on page 81 ATmega8(L) 80 (1) (1) 1. See “About Code Examples” on page 8 shows a block diagram of the counter and its surroundings ...
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... Signalize that TCNT1 has reached minimum value (zero) ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear ATmega8(L) TOVn (Int. Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) ...
Page 82
... Input Capture Pin The main trigger source for the Input Capture unit is the Input Capture Pin (ICP1). Timer/Counter Source 1 can alternatively use the Analog Comparator Output as trigger source for the Input Capture ATmega8(L) 82 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ...
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... A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (that is counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the waveform generator. 2486Z–AVR–02/11 (Figure 30 on page “Modes of Operation” on page 87). ATmega8(L) 73). The edge detector is also 83 ...
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... High byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Com- pare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to on page ATmega8(L) 84 shows a block diagram of the Output Compare unit. The small “n” in the register and DATA BUS TEMP (8-bit) OCRnxH Buf ...
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... Registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin System Reset occur, the OC1x Register is reset to “0”. 2486Z–AVR–02/11 ATmega8(L) Figure 36 on page 86 shows a 85 ...
Page 86
... The design of the Output Compare Pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of oper- ation. See “16-bit Timer/Counter Register Description” on page 96. The COM1x1:0 bits have no effect on the Input Capture unit. ATmega8(L) 86 COMnx1 Waveform COMnx0 ...
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... Compare Match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. 2486Z–AVR–02/11 Table 36 on page See “Compare Match Output Unit” on page 85. “Timer/Counter Timing Diagrams” on page ATmega8(L) 96. For fast PWM mode refer to Table 38 on page 94. Figure 37 on page 88. The counter value ...
Page 88
... High frequency allows physically small sized external components (coils, capaci- tors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-bit, 9-bit, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the ATmega8( when OCR1A is set to zero (0x0000) ...
Page 89
... TCNT1 is cleared and the TOV1 Flag is set. 2486Z–AVR–02/11 ( TOP log R = ---------------------------------- - FPWM log ATmega8( Figure 38. The figure shows OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...
Page 90
... The timing diagram for the phase correct PWM mode is shown on The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope opera- ATmega8(L) 90 Table 37 on page ...
Page 91
... Compare Match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at Compare Match between OCR1x and TCNT1 when 2486Z–AVR–02/ Figure 39 ATmega8(L) OCRnx / TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) ...
Page 92
... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs. ATmega8( OCnxPCPWM ...
Page 93
... PWM mode. If the OCR1x is set equal to BOTTOM the 2486Z–AVR–02/ shows the output generated is, in contrast to the Phase Correct mode, symmetrical f OCnxPFCPWM ATmega8(L) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) (COMnx1 ...
Page 94
... Figure 42. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 43 on page 95 phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The tim- ATmega8(L) 94 Figure 41 I/O Tn /1) I/O OCRnx - 1 shows the same timing data, but with the prescaler enabled. ...
Page 95
... I/O clk Tn (clk /8) I/O TCNTn TOP - 1 TCNTn TOP - 1 (FPWM) (if used as TOP) OCRnx Old OCRnx Value ATmega8(L) TOP BOTTOM BOTTOM + 1 TOP TOP - 1 New OCRnx Value /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 New OCRnx Value TOP - 2 TOP - 2 ...
Page 96
... WGM13:0 bits are set to a normal or a CTC mode (non-PWM). Table 36. Compare Output Mode, Non-PWM COM1A1/ COM1B1 Table 37 mode. Table 37. Compare Output Mode, Fast PWM COM1A1/ COM1B1 Note: ATmega8( COM1A1 COM1A0 COM1B1 COM1B0 R/W R/W R/W R Table 36 ...
Page 97
... PWM, Phase Correct, 8-bit 1 0 PWM, Phase Correct, 9-bit 1 1 PWM, Phase Correct, 10-bit 0 0 CTC 0 1 Fast PWM, 8-bit 1 0 Fast PWM, 9-bit ATmega8(L) for more details “Modes of Operation” on page 87). Update of x TOP OCR1 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP ...
Page 98
... TCCR1B is written. • Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A Register description. • Bit 2:0 – CS12:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter, see 41 on page 94 ATmega8(L) 98 WGM10 Timer/Counter Mode of (1) (PWM10) ...
Page 99
... External clock source on T1 pin. Clock on rising edge TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R ATmega8( TCNT1H TCNT1L R/W R/W R/W R See “Accessing 16-bit OCR1AH OCR1AL R/W R/W R/W R OCR1BH OCR1BL R/W R/W R/W R ...
Page 100
... Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page ATmega8(L) 100 See “Accessing 16-bit Registers” on page 77 ...
Page 101
... OCF2 TOV2 ICF1 OCF1A R/W R/W R/W R This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections ATmega8( OCF1B TOV1 – TOV0 R/W R ...
Page 102
... I/O pins, refer to including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the Figure 45. 8-bit Timer/Counter Block Diagram Status Flags ATmega8(L) 102 “Pin Configurations” on page “8-bit Timer/Counter Register Description” on page TCCRn ...
Page 103
... The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The assignment is dependent on the mode of operation default equal to the MCU clock, clk T2 117. For details on clock sources and prescaler, see 120. ATmega8(L) “Output . When the AS2 I/O “Asyn- 103 ...
Page 104
... OC2. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page The Timer/Counter Overflow (TOV2) Flag is set according to the mode of operation selected by the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt. ATmega8(L) 104 DATA BUS count ...
Page 105
... CPU has access to the OCR2 Buffer Register, and if double buffering is disabled the CPU will access the OCR2 directly. 2486Z–AVR–02/11 108). shows a block diagram of the Output Compare unit. DATA BUS OCRn = (8-bit Comparator ) TOP BOTTOM Waveform Generator FOCn WGMn1:0 ATmega8(L) TCNTn OCFn (Int. Req.) OCxy COMn1:0 “Modes of 105 ...
Page 106
... Normal mode. The OC2 Register keeps its value even when changing between waveform generation modes. Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the COM21:0 bits will take effect immediately. ATmega8(L) 106 2486Z–AVR–02/11 ...
Page 107
... Note that some COM21:0 bit settings are reserved for certain modes of operation. 2486Z–AVR–02/11 COMn1 Waveform COMn0 Generator FOCn clk I/O See “8-bit Timer/Counter Register Description” on page 114. ATmega8(L) Figure 48 shows a simplified sche OCn Pin OCn 0 D ...
Page 108
... The Output Compare unit can be used to generate interrupts at some given time. Using the Out- put Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. ATmega8(L) 108 Table 43 on page 115. For fast PWM mode, refer to Table 45 on page “ ...
Page 109
... As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 2486Z–AVR–02/11 Figure clk_I ---------------------------------------------- - OCn ⋅ ⋅ OCRn 1 + ATmega8(L) 49. The counter value (TCNT2) OCn Interrupt Flag Set (COMn1 OC2 clk_I/O ) 109 /2 ...
Page 110
... MAX to BOTTOM). The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). ATmega8(L) 110 Figure 50. The TCNT2 value is in the timing diagram shown as a histo- ...
Page 111
... TCNT2 slopes represent compare matches between OCR2 and TCNT2. Figure 51. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period 2486Z–AVR–02/ when OCR2 is set to zero. This fea- oc2 clk_I ATmega8(L) Figure 51. OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 111 ...
Page 112
... MAX value in all modes other than phase correct PWM mode. Figure 52. Timer/Counter Timing Diagram, no Prescaling clk clk (clk TCNTn TOVn ATmega8(L) 112 f OCnPCPWM Figure 51 on page 111 contains timing data for basic Timer/Counter operation. The figure shows the I/O ...
Page 113
... OCRn OCFn 2486Z–AVR–02/11 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O MAX - 1 shows the setting of OCF2 in all modes except CTC mode. I/O Tn /8) I/O OCRn - 1 ATmega8(L) /8) clk_I/O MAX BOTTOM OCRn OCRn + 1 OCRn Value BOTTOM + 1 /8) clk_I/O OCRn + 2 113 ...
Page 114
... Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Operation” on page ATmega8(L) 114 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. /8) ...
Page 115
... Set OC2 on Compare Match, clear OC2 at BOTTOM, (inverting mode special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See for more details ATmega8(L) Update of (1) TOP OCR2 ...
Page 116
... The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC2 pin. ATmega8(L) 116 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct ...
Page 117
... When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not 2486Z–AVR–02/ – – – – AS2 R ATmega8( TCN2UB OCR2UB TCR2UB ASSR When AS2 is I/O 117 ...
Page 118
... The recommended procedure for reading TCNT2 is thus as follows: 1. Write any value to either of the registers OCR2 or TCCR2 2. Wait for the corresponding Update Busy Flag to be cleared 3. Read TCNT2 ATmega8(L) 118 ) again becomes active, TCNT2 will read as the previous I/O 2486Z–AVR–02/11 ...
Page 119
... PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. 2486Z–AVR–02/ OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B R/W R/W R/W R/W R OCF2 TOV2 ICF1 OCF1A OCF1B R/W R/W R/W R/W R ATmega8( TOIE1 – TOIE0 TIMSK R TOV1 – TOV0 TIFR R 119 ...
Page 120
... Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in Asynchronous mode, the bit will remain one until the prescaler has been reset. ATmega8(L) 120 clk clk ...
Page 121
... Serial The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8 and peripheral devices or between several AVR devices. The ATmega8 SPI includes Peripheral the following features: Interface – SPI • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • ...
Page 122
... High period: longer than 2 CPU clock cycles When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 47. SPI Pin Overrides Pin MOSI MISO SCK SS Note: ATmega8(L) 122 MSB MASTER LSB MISO 8 BIT SHIFT REGISTER MOSI SPI SCK SS ...
Page 123
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See “About Code Examples” on page 8 ATmega8(L) 123 ...
Page 124
... DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) /* Return data register */ return SPDR; } Note: ATmega8(L) 124 (1) r17,(1<<DD_MISO) DDR_SPI,r17 r17,(1<<SPE) SPCR,r17 r16,SPDR ( See “About Code Examples” on page 8 2486Z–AVR–02/11 ...
Page 125
... When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. 2486Z–AVR–02/ SPIE SPE DORD MSTR CPOL R/W R/W R/W R/W R ATmega8( CPHA SPR1 SPR0 SPCR R/W R/W R 125 ...
Page 126
... Slave. The relationship between SCK and the Oscillator Clock frequency f shown in the following table: Table 50. Relationship Between SCK and the Oscillator Frequency SPI2X SPI Status Register – SPSR Bit Read/Write Initial Value ATmega8(L) 126 Figure 59 on page 128 Leading Edge 0 Rising 1 Falling Figure 59 on page 128 ...
Page 127
... Master mode (see 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. osc The SPI interface on the ATmega8 is also used for Program memory and EEPROM download- ing or uploading. See SPI Data Register – SPDR Bit ...
Page 128
... Figure 59. SPI Transfer Format with CPHA = 0 MSB first (DORD = 0) LSB first (DORD = 1) Figure 60. SPI Transfer Format with CPHA = 1 ATmega8(L) 128 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB Bit 6 Bit 5 LSB Bit 1 Bit 2 SCK (CPOL = 0) ...
Page 129
... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. Refer to “Pin Configurations” on page USART pin placement ATmega8(L) Figure 61. CPU accessible I/O Clock Generator OSC SYNC LOGIC PIN CONTROL Transmitter TX CONTROL PARITY GENERATOR ...
Page 130
... When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using Synchronous mode. Figure 62 on page 131 ATmega8(L) 130 shows a block diagram of the clock generation logic. Figure 61 on page 129) if the Buffer 2486Z– ...
Page 131
... Input from XCK pin (internal Signal). Used for synchronous slave operation Clock output to XCK pin (Internal Signal). Used for synchronous master operation XTAL pin frequency (System Clock) contains equations for calculating the baud rate (in bits per second) and ATmega8(L) U2X / ...
Page 132
... The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. ATmega8(L) 132 Equation for Calculating ...
Page 133
... Bits inside brackets are (IDLE Start bit, always low Data bits ( Parity bit. Can be odd or even Stop bit, always high No transfers on the communication line (RxD or TxD). An IDLE line must be high ATmega8(L) Sample Sample FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) ...
Page 134
... The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Regis- ters. When the function writes to the UCSRC Register, the URSEL bit (MSB) must be set due to the sharing of I/O location by UBRRH and UCSRC. ATmega8(L) 134 ⊕ … ...
Page 135
... UCSRC,r16 out ret (1) ... USART_Init ( MYUBRR ); ... /* Set baud rate */ UBRRH = (unsigned char)(ubrr>>8); UBRRL = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSRB = (1<<RXEN)|(1<<TXEN); /* Set frame format: 8data, 2stop bit */ UCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0); 1. See “About Code Examples” on page 8 ATmega8(L) 135 ...
Page 136
... UDR = data; } Note: The function simply waits for the transmit buffer to be empty by checking the UDRE Flag, before loading it with new data to be transmitted. If the Data Register Empty Interrupt is utilized, the interrupt routine writes the data into the buffer. ATmega8(L) 136 (1) UDR,r16 (1) ; ...
Page 137
... UCSRB |= (1<<TXB8); /* Put data into buffer, sends the data */ UDR = data; 1. These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSRB is static. That is, only the TXB8 bit of the UCSRB Register is used after initialization ATmega8(L) 137 ...
Page 138
... Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDR I/O location. The following code example shows a simple USART receive function based on polling of the Receive Complete (RXC) Flag. When using frames with less than eight bits the most significant ATmega8(L) 138 2486Z–AVR–02/11 ...
Page 139
... UCSRA, RXC rjmp USART_Receive ; Get and return received data from buffer in r16, UDR ret (1) /* Wait for data to be received */ while ( !(UCSRA & (1<<RXC Get and return received data from buffer */ return UDR; 1. See “About Code Examples” on page 8 ATmega8(L) 139 ...
Page 140
... Note: The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. ATmega8(L) 140 (1) r18, UCSRA r17, UCSRB ...
Page 141
... The PE bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. 2486Z–AVR–02/11 and “Parity Checker” . ATmega8(L) 141 ...
Page 142
... Sample (U2X = 0) Sample (U2X = 1) When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in ATmega8(L) 142 (1) r16, UDR (1) 1. See “About Code Examples” on page 8 ...
Page 143
... Figure 67. For Double Speed mode the first low level must be delayed to (B). ATmega8(L) shows the sampling of the data bits and the BIT ...
Page 144
... Normal Speed mode has higher toleration of baud rate variations. Table 53. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) (Data + Parity Bit) Table 54. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (Data + Parity Bit) ATmega8(L) 144 ( ) ...
Page 145
... Transmitter and Receiver uses the same character size set- ting. If 5-bit to 8-bit character frames are used, the Transmitter must be set to use two stop bit (USBS = 1) since the first stop bit is used for indicating the frame type. 2486Z–AVR–02/11 ATmega8(L) 145 ...
Page 146
... Set the USBS and the UCSZ1 bit to one, and */ /* the remaining bits to zero. */ UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1); ... Note: As the code examples illustrate, write accesses of the two registers are relatively unaffected of the sharing of I/O location. ATmega8(L) 146 (1) (1) 1. See “About Code Examples” on page 8 2486Z–AVR–02/11 ...
Page 147
... Reading the UBRRH contents is not an atomic operation and therefore it can be read as an ordi- nary register, as long as the previous instruction did not access the register location. 2486Z–AVR–02/11 (1) ; Read UCSRC in r16,UBRRH in r16,UCSRC ret (1) unsigned char ucsrc; /* Read UCSRC */ ucsrc = UBRRH; ucsrc = UCSRC; return ucsrc; 1. See “About Code Examples” on page 8 ATmega8(L) 147 ...
Page 148
... The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is one, the buffer is empty, and therefore ready to be written. The UDRE Flag can generate a Data Register Empty interrupt (see description of the Interrupt Enable” on page UDRE is set after a reset to indicate that the Transmitter is ready. ATmega8(L) 148 ...
Page 149
... RxD pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FE, DOR and PE Flags. 2486Z–AVR–02/11 “Multi-processor Communication Mode” on page RXCIE TXCIE UDRIE RXEN TXEN R/W R/W R/W R ATmega8(L) 145 UCSZ2 RXB8 TXB8 UCSRB R/W R 149 ...
Page 150
... This bit selects between accessing the UCSRC or the UBRRH Register read as one when reading UCSRC. The URSEL must be one when writing the UCSRC. • Bit 6 – UMSEL: USART Mode Select This bit selects between Asynchronous and Synchronous mode of operation. Table 55. UMSEL Bit Settings ATmega8(L) 150 ...
Page 151
... Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity USBS 0 1 UCSZ1 ATmega8(L) Stop Bit(s) 1-bit 2-bit UCSZ0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit 151 ...
Page 152
... UBRRL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler. ATmega8(L) 152 Transmitted Data Changed ...
Page 153
... Error UBRR Error 0.2% 47 0.0% 0.2% 23 0.0% 0.2% 11 0.0% -3.5% 7 0.0% -7.0% 5 0.0% 8.5% 3 0.0% 8.5% 2 0.0% 8.5% 1 0.0% -18.6% 1 -25.0% 8.5% 0 0.0% – – – – – – 125kbps 115.2kbps ATmega8(L) Table “Asynchronous Operational ⎞ Closest Match • – 100% ⎠ BaudRate f = 2.0000MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 95 0.0% 51 0.2% 47 0.0% 25 0.2% 23 0.0% 12 0.2% 15 0.0% 8 -3.5% 11 0.0% 6 -7. ...
Page 154
... Max 230.4kbps 460.8kbps 1. UBRR = 0, Error = 0.0% ATmega8(L) 154 f = 4.0000MHz osc U2X = 0 U2X = 1 Error UBRR Error UBRR 0.0% 103 0.2% 207 0.0% 51 0.2% 103 0.0% 25 0.2% 51 0.0% 16 2.1% 34 0.0% 12 0.2% 25 0.0% 8 -3.5% 16 0.0% 6 -7.0% 12 0.0% 3 8. ...
Page 155
... U2X = 1 U2X = 0 Error UBRR Error -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% 0.2% 17 0.0% 2.1% 11 0.0% 0.2% 8 0.0% -3.5% 5 0.0% 8.5% 2 0.0% 0.0% 2 -7.8% 0.0% – – 0.0% – – 691.2kbps 1.3824Mbps ATmega8(L) MHz f = 14.7456MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0.0% 95 0.0% 95 0.0% 63 0.0% 71 0.0% 47 0.0% 47 0.0% 31 0.0% 35 0.0% 23 0.0% 23 0.0% 15 0.0% 17 0.0% 11 0.0% 11 0.0% 7 ...
Page 156
... Max 1Mbps 1. UBRR = 0, Error = 0.0% ATmega8(L) 156 f = 18.4320MHz osc U2X = 0 Error UBRR Error UBRR 0.0% 479 0.0% -0.1% 239 0.0% 0.2% 119 0.0% -0.1% 79 0.0% 0.2% 59 0.0% 0.6% 39 0.0% 0.2% 29 0.0% -0.8% 19 0.0% 0.2% 14 0.0% 2.1% 9 0.0% -3.5% 4 0.0% 0.0% 4 -7.8% 0.0% – – 0.0% – – ...
Page 157
... Device 3 SDA SCL Description The device that initiates and terminates a transmission. The Master also generates the SCL clock The device addressed by a Master The device placing data on the bus The device reading data from the bus ATmega8( ........ Device 157 ...
Page 158
... START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. ATmega8(L) 158 Figure 68 on page 157, both bus lines are connected to the positive supply volt- “ ...
Page 159
... All addresses of the format 1111 xxx should be reserved for future purposes. Figure 71. Address Packet Format SDA SCL 2486Z–AVR–02/11 START STOP Addr MSB 1 2 START ATmega8(L) START REPEATED START Addr LSB R/W ACK STOP 159 ...
Page 160
... SLA+R/W and the STOP condition, depending on the software protocol imple- mented by the application software. Figure 73. Typical Data Transmission Addr MSB SDA SCL 1 2 START SLA+R/W ATmega8(L) 160 Data MSB 1 2 SLA+R/W shows a typical data transmission. Note that several data bytes can be transmitted Addr LSB R/W ACK ...
Page 161
... Arbitration will continue until only one Master remains, and this may take many bits. If several masters are trying to address the same Slave, arbitration will continue into the data packet. 2486Z–AVR–02/11 TA low Line TB Masters Start Counting Low Period ATmega8(L) TA high TB low high Masters Start Counting High Period 161 ...
Page 162
... This implies that in multi-master systems, all data transfers must use the same composi- tion of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. ATmega8(L) 162 START SDA from ...
Page 163
... Bus Interface Unit START / STOP Spike Suppression Control Address/Data Shift Arbitration detection Register (TWDR) Address Match Unit Address Register (TWAR) Address Comparator ATmega8(L) Figure 76. All registers drawn Spike Filter Bit Rate Generator Prescaler Bit Rate Register Ack (TWBR) Control Unit Status Register ...
Page 164
... TWSR contains a special status code indicating that no relevant status information is avail- able. As long as the TWINT Flag is set, the SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to continue. ATmega8(L) 164 SCL frequency Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load ...
Page 165
... TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 R/W R/W R/W R for calculating bit rates TWINT TWEA TWSTA TWSTO TWWC R/W R/W R/W R ATmega8( TWBR2 TWBR1 TWBR0 TWBR R/W R/W R/W R “Bit Rate Generator TWEN – TWIE TWCR R R ...
Page 166
... Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should mask the pres- caler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. ATmega8(L) 166 7 6 ...
Page 167
... TWD7 TWD6 TWD5 TWD4 TWD3 R/W R/W R/W R TWA6 TWA5 TWA4 TWA3 TWA2 R/W R/W R/W R ATmega8(L) 164. The value of TWPS1.. TWD2 TWD1 TWD0 TWDR R/W R/W R/W R TWA1 TWA0 TWGCE TWAR R/W R/W R/W R 167 ...
Page 168
... When the START condition has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the START condition has success- fully been sent ATmega8(L) 168 is a simple example of how the application can interface to the TWI hardware. In this 5 ...
Page 169
... TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting In the following an assembly and C implementation of the example is given. Note that the code below assumes that several definitions have been made, for example by using include-files. 2486Z–AVR–02/11 ATmega8(L) 169 ...
Page 170
... MT_DATA_ACK cpi brne ERROR ldi r16, (1<<TWINT)|(1<<TWEN)| (1<<TWSTO) out TWCR, r16 ATmega8(L) 170 C Example TWCR = (1<<TWINT)|(1<<TWSTA)| (1<<TWEN) while (!(TWCR & (1<<TWINT))) ; if ((TWSR & 0xF8) != START) ERROR(); TWDR = SLA_W; TWCR = (1<<TWINT) | (1<<TWEN); while (!(TWCR & (1<<TWINT))) ...
Page 171
... Figure 85 on page 183, circles are used to indicate that the TWINT Table 66 on page 173 to Table 69 on page 172). In order to enter a Master mode, a START condition must be ATmega8(L) 182. Note that the prescaler bits 171 ...
Page 172
... A REPEATED START condition is generated by writing the following value to TWCR: TWCR value After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same Slave again new Slave without transmitting a STOP condition. Repeated START ATmega8(L) 172 Device 1 Device 2 Device 3 ...
Page 173
... No TWDR action TWDR action ATmega8(L) TWEA Next Action Taken by TWI Hardware X SLA+W will be transmitted; ACK or NOT ACK will be received X SLA+W will be transmitted; ACK or NOT ACK will be received X SLA+R will be transmitted; Logic will switch to Master Receiver mode ...
Page 174
... Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost in slave address or data byte Arbitration lost and addressed as slave ATmega8(L) 174 MT S SLA W A $08 $18 A $20 Other master $38 ...
Page 175
... Table 67 on page 176. Received data can be read from the TWDR Register when TWINT TWEA TWSTA TWSTO TWINT TWEA TWSTA TWSTO ATmega8( ........ Device TWWC TWEN – TWIE Table 66 on page 173). In order to enter TWWC TWEN – ...
Page 176
... SLA+R has been transmitted; NOT ACK has been received 0x50 Data byte has been received; ACK has been returned 0x58 Data byte has been received; NOT ACK has been returned ATmega8(L) 176 Application Software Response To TWCR To/from TWDR STA STO TWINT ...
Page 177
... All the status codes mentioned in this section assume that the prescaler bits are Device 1 Device 2 Device 3 SLAVE MASTER RECEIVER TRANSMITTER SDA SCL TWA6 TWA5 TWA4 TWA3 Device’s Own Slave Address ATmega8(L) A DATA A P $50 $58 R SLA S $10 Other master A continues $38 To corresponding ...
Page 178
... Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions. Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these Sleep modes. ATmega8(L) 178 TWINT TWEA ...
Page 179
... ATmega8(L) TWEA Next Action Taken by TWI Hardware 0 Data byte will be received and NOT ACK will be re- turned 1 Data byte will be received and ACK will be returned 0 Data byte will be received and NOT ACK will be re- turned 1 ...
Page 180
... Last data byte received is not acknowledged Arbitration lost as master and addressed as slave Reception of the general call address and one or more data bytes Last data byte received is not acknowledged Arbitration lost as master and addressed as slave by general call ATmega8(L) 180 S SLA W A $60 A $68 General Call A ...
Page 181
... All the status codes mentioned in this section assume that the prescaler bits are Device 1 Device 2 Device 3 SLAVE MASTER TRANSMITTER RECEIVER SDA SCL TWA6 TWA5 TWA4 TWA3 Device’s Own Slave Address TWINT TWEA TWSTA TWSTO ATmega8( ........ Device TWA2 TWA1 TWA0 TWWC TWEN – TWGCE TWIE X Table 69 on 181 ...
Page 182
... Data byte in TWDR has been transmitted; NOT ACK has been received 0xC8 Last data byte in TWDR has been transmitted (TWEA = “0”); ACK has been received ATmega8(L) 182 Application Software Response To TWCR To/from TWDR STA STO TWINT Load data byte or ...
Page 183
... From master to slave From slave to master n Application Software Response To TWCR To/from TWDR STA STO TWINT No TWDR action No TWCR action No TWDR action ATmega8(L) DATA A DATA $B8 $C0 A All 1's $C8 Any number of data bytes A and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-Wire Serial Bus ...
Page 184
... Several different scenarios may arise during arbitration, as described below: • Two or more masters are performing identical communication with the same Slave. In this case, neither the Slave nor any of the masters will know about the bus contention ATmega8(L) 184 Master Transmitter SLA+W ...
Page 185
... No Address / General Call received Yes Write Direction Read ATmega8(L) Data Arbitration lost in Data 38 TWI bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free 68/78 Data byte will be received and NOT ACK will be returned ...
Page 186
... ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see Analog Comparator Control and Status Bit Register – ACSR Read/Write Initial Value ATmega8(L) 186 Figure 89. ACBG (1) OUTPUT 1. See Table 72 on page 188 2. Refer to “ ...
Page 187
... Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. 2486Z–AVR–02/11 Table 71. ACIS0 Interrupt Mode 0 Comparator Interrupt on Output Toggle 1 Reserved 0 Comparator Interrupt on Falling Output Edge 1 Comparator Interrupt on Rising Output Edge ATmega8(L) 187 ...
Page 188
... Analog Comparator, as shown in 72. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog Comparator. Table 72. Analog Comparator Multiplexed Input ACME Note: ATmega8(L) 188 ADEN MUX2..0 Analog Comparator Negative Input x xxx AIN1 1 xxx AIN1 0 000 ADC0 0 001 ...
Page 189
... Interrupt on ADC Conversion Complete • Sleep Mode Noise Canceler The ATmega8 features a 10-bit successive approximation ADC. The ADC is connected channel Analog Multiplexer which allows eight single-ended voltage inputs constructed from the pins of Port C. The single-ended voltage inputs refer to 0V (GND). ...
Page 190
... The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX. ATmega8(L) 190 8-BIT DATA BUS ADC MULTIPLEXER ...
Page 191
... ADC clock cycle. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. 2486Z–AVR–02/11 ADEN Reset START 7-BIT ADC PRESCALER CK ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE ATmega8(L) 191 ...
Page 192
... Figure 92. ADC Timing Diagram, First Conversion (Single Conversion Mode) Cycle Number ADC Clock ADEN ADSC ADIF ADCH ADCL Figure 93. ADC Timing Diagram, Single Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL ATmega8(L) 192 First Conversion MUX and REFS Sample & Hold ...
Page 193
... One Conversion Next Conversion Cycle Number ADC Clock ADSC ADIF ADCH MSB of Result ADCL LSB of Result Conversion Complete MUX and REFS Update Sample & Hold (Cycles from Start of Conversion) 13.5 1.5 ATmega8( Sample &Hold Conversion Time (Cycles 193 ...
Page 194
... AREF pin, the user may switch between AV reference selection. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. ATmega8(L) 194 ) indicates the conversion range for the ADC. Single REF will result in codes close to 0x3FF ...
Page 195
... CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in Active mode until a new sleep command is executed I IH ADCn I IL ATmega8(L) /2) should not be present for either ADC 1..100kΩ 14pF S ...
Page 196
... Several parameters describe the deviation from the ideal behavior: • Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB ATmega8(L) 196 ground plane, and keep them well away from high-speed switching digital tracks. pin on the device should be connected to the digital V ...
Page 197
... Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 98. Gain Error 2486Z–AVR–02/11 Output Code Offset Error Output Code ATmega8(L) Ideal ADC Actual ADC V Input Voltage REF Gain Error Ideal ADC ...
Page 198
... Absolute accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value: ±0.5 LSB. ATmega8(L) 198 Output Code Output Code 0x3FF ...
Page 199
... AV 1 with external capacitor at AREF pin CC 0 Reserved 1 Internal 2.56V Voltage Reference with external capacitor at AREF pin Single Ended Input ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ATmega8(L) ⋅ V 1024 IN = -------------------------- V REF the selected voltage reference (see REF MUX3 ...
Page 200
... Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. • Bit 3 – ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter- rupt is activated. ATmega8(L) 200 Single Ended Input ADC6 ADC7 1 ...