ATmega8 Atmel Corporation, ATmega8 Datasheet - Page 127

• Manufacturer Part Number: ATmega8
• Manufacturer: Atmel Corporation

Specifications of ATmega8

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

SPI Data Register –
SPDR
Data Modes
2486Z–AVR–02/11
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the
corresponding interrupt Handling Vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the ATmega8 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see
2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at
f
The SPI interface on the ATmega8 is also used for Program memory and EEPROM download-
ing or uploading. See
The SPI Data Register is a Read/Write Register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-
ter causes the Shift Register Receive buffer to be read.
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
59 on page 128
edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen
by summarizing
Table 51. CPOL and CPHA Functionality
osc
Bit
Read/Write
Initial Value
/4 or lower.
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
MSB
R/W
X
7
and
Table 48 on page 126
Figure 60 on page
page 230
R/W
Table 50 on page
X
6
Sample (Falling)
Sample (Rising)
Leading Edge
Setup (Rising)
Setup (Falling)
R/W
for Serial Programming and verification.
5
X
and
R/W
128. Data bits are shifted out and latched in on opposite
4
X
126). This means that the minimum SCK period will be
Table 49 on page
R/W
X
3
Sample (Falling)
Sample (Rising)
Setup (Falling)
Trailing Edge
Setup (Rising)
R/W
X
2
126, as done below:
R/W
X
1
LSB
R/W
ATmega8(L)
0
X
SPI Mode
0
1
2
3
Undefined
SPDR
Figure
127