ATmega8 Atmel Corporation, ATmega8 Datasheet - Page 43

• Manufacturer Part Number: ATmega8
• Manufacturer: Atmel Corporation

Specifications of ATmega8

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Watchdog Timer
Watchdog Timer
Control Register –
WDTCR
2486Z–AVR–02/11
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This is
the typical value at V
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as
shown in
Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the ATmega8 resets and executes from the
Reset Vector. For timing details on the Watchdog Reset, refer to
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be fol-
lowed when the Watchdog is disabled. Refer to
for details.
Figure 20. Watchdog Timer
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega8 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to
3 – WDE: Watchdog Enable” on page
and 2, this bit must also be set when changing the prescaler bits. See the Code Examples on
page
Bit
Read/Write
Initial Value
45.
Table 17 on page
R
7
–
0
CC
OSCILLATOR
= 5V. See characterization data for typical values at other V
WATCHDOG
R
6
–
0
44. The WDR – Watchdog Reset – instruction resets the Watchdog
R
5
–
0
WDCE
R/W
44for a Watchdog disable procedure. In Safety Level 1
4
0
WDE
R/W
“Watchdog Timer Control Register – WDTCR”
3
0
WDP2
R/W
2
0
WDP1
R/W
page
1
0
41.
WDP0
R/W
ATmega8(L)
0
0
WDTCR
CC
levels. By
“Bit
43