ATmega8 Atmel Corporation, ATmega8 Datasheet - Page 239

• Manufacturer Part Number: ATmega8
• Manufacturer: Atmel Corporation

Specifications of ATmega8

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

SPI Timing
Characteristics
2486Z–AVR–02/11
5. This requirement applies to all ATmega8 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial
6. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/f
7. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/f
Bus need only obey the general f
6MHz for the low time requirement to be strictly met at f
will not be strictly met for f
full speed (400kHz) with other ATmega8 devices, as well as any other device with a proper t
Figure 115. Two-wire Serial Bus Timing
See
Table 102. SPI Timing Parameters
Note:
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
SCL
SDA
Figure 116 on page 240
SCL
1. In SPI Programming mode the minimum SCK high/low period is:
SS high to tri-state
t
SU;STA
> 308kHz when f
SCK to out high
SCK to SS high
- 2t
- 3t
SCK high/low
SS low to SCK
SCK high/low
Rise/Fall time
Rise/Fall time
SS low to out
Description
SCK period
Out to SCK
SCK period
SCK to out
SCK to out
CLCL
CLCL
SCL
Setup
Setup
Hold
Hold
requirement
for f
for f
CK
CK
(1)
< 12MHz
> 12MHz
t
CK
HD;STA
= 8MHz. Still, ATmega8 devices connected to the bus may communicate at
t
and
of
t
LOW
Master
Master
Master
Master
Master
Master
Master
Master
Figure 117 on page 240
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Salve
SCL
= 100kHz
t
HIGH
t
HD;DAT
4 • t
2 • t
2 • t
Min
10
10
20
ck
ck
ck
t
LOW
See
t
50% duty cycle
SU;DAT
SCL
page 126
SCL
for details.
0.5 • t
Table 50 on
Typ
3.6
10
10
10
10
15
15
10
- 2/f
- 2/f
SCK
CK
CK
), thus the low time requirement
), thus f
LOW
acceptance margin
ATmega8(L)
CK
Max
1600
t
SU;STO
must be greater than
t
r
ns
t
BUF
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