ATmega8 Atmel Corporation, ATmega8 Datasheet - Page 14

• Manufacturer Part Number: ATmega8
• Manufacturer: Atmel Corporation

Specifications of ATmega8

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Reset and
Interrupt Handling
14
ATmega8(L)
Figure 5
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 5. The Parallel Instruction Fetches and Instruction Executions
Figure 6
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 6. Single Cycle ALU Operation
The Atmel
Reset Vector each have a separate Program Vector in the Program memory space. All inter-
rupts are assigned individual enable bits which must be written logic one together with the
Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on
the Program Counter value, interrupts may be automatically disabled when Boot Lock Bits
BLB02 or BLB12 are programmed. This feature improves software security. See the section
“Memory Programming” on page 215
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of Vectors is shown in
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the boot Flash section by setting the Inter-
rupt Vector Select (IVSEL) bit in the General Interrupt Control Register (GICR). Refer to
“Interrupts” on page 46
the boot Flash section by programming the BOOTRST Fuse, see
While-Write Self-Programming” on page
2nd Instruction Execute
Register Operands Fetch
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
shows the parallel instruction fetches and instruction executions enabled by the Har-
shows the internal timing concept for the Register File. In a single clock cycle an ALU
®
Result Write Back
AVR
®
provides several different interrupt sources. These interrupts and the separate
clk
clk
CPU
CPU
for more information. The Reset Vector can also be moved to the start of
T1
T1
for details.
202.
T2
T2
“Interrupts” on page
“Boot Loader Support – Read-
T3
T3
46. The list also
2486Z–AVR–02/11
T4
T4