ATmega8 Atmel Corporation, ATmega8 Datasheet - Page 206

• Manufacturer Part Number: ATmega8
• Manufacturer: Atmel Corporation

Specifications of ATmega8

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Store Program
Memory Control
Register – SPMCR
206
ATmega8(L)
Table 80. Boot Reset Fuse
Note:
The Store Program memory Control Register contains the control bits needed to control the Boot
Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN
bit in the SPMCR Register is cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-Programming (page erase or page write) operation to the RWW section is initiated,
the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section can-
not be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a
Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be
cleared if a page load operation is initiated.
• Bit 5 – Res: Reserved Bit
This bit is a reserved bit in the ATmega8 and always read as zero.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
When programming (page erase or page write) to the RWW section, the RWW section is
blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the
user software must wait until the programming is completed (SPMEN will be cleared). Then, if
the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within
four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while
the Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is writ-
ten while the Flash is being loaded, the Flash load operation will abort and the data loaded will
be lost (The page buffer will be cleared when the Read-While-Write section is re-enabled).
• Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles sets Boot Lock Bits, according to the data in R0. The data in R1 and the address in the Z-
pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit
set, or if no SPM instruction is executed within four clock cycles.
An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR Regis-
ter, will read either the Lock Bits or the Fuse Bits (depending on Z0 in the Z-pointer) into the
destination register. See
details.
Bit
Read/Write
Initial Value
BOOTRST
1
0
1. “1” means unprogrammed, “0” means programmed
SPMIE
R/W
7
0
Reset Address
Reset Vector = Application Reset (address 0x0000)
Reset Vector = Boot Loader Reset (see
RWWSB
R
6
0
“Reading the Fuse and Lock Bits from Software” on page 210
(1)
R
5
–
0
RWWSRE
R/W
4
0
BLBSET
R/W
3
0
Table 82 on page
PGWRT
R/W
2
0
PGERS
R/W
1
0
213)
SPMEN
R/W
0
0
SPMCR
2486Z–AVR–02/11
for