ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 250

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.13.12 INTFLAGSBCLR/ INTFLAGSBSET – Clear/ Set Interrupt Flag Register B
8331A–AVR–07/11
Both memory locations will provide the same result when read, and writing zero to any bit loca-
tion has no effect.
• Bit 7 – SOFIF: Start Of Frame Interrupt Flag
This flag is set when a Start of Frame packet has been received.
• Bit 6 – SUSPENDIF: Suspend Interrupt Flag
This flag is set when the bus has been idle for 3ms.
• Bit 5 – RESUMEIF: Resume Interrupt Flag
This flag is set when a non-idle state has been detected on the bus while the USB module is in
the suspend state. This interrupt is asynchronous, and is able to wake the CPU from sleep
modes where the system clock is stopped such as Power-down and Power-save sleep modes.
• Bit 4 – RSTIF: Reset Interrupt Flag
This flag is set when a reset condition has been detected on the bus.
• Bit 3 – CRCIF: Isochronous CRC Error Interrupt Flag
This flag is set when a CRC error has been detected in an incoming data packet to an isochro-
nous endpoint.
• Bit 2 – UNFIF: Underflow Interrupt Flag
This flag is set when the addressed endpoint in an IN transaction does not have data to send to
the host.
• Bit 1 – OVFIF: Overflow Interrupt Flag
This flag is set when the addressed endpoint in an OUT transaction is not ready to accept data
from the host.
• Bit 0 – STALLIF: STALL Interrupt Flag
This flag is set when the USB module has responded with a STALL handshake to either an IN or
an OUT transaction.
This register is mapped into two I/O memory locations, one for clearing (INTFLAGSBCLR) and
one for setting the flags (INTFLAGSBSET). The individual flags can be set by writing a one to its
bit location in INFLAGSBSET, and cleared by writing a one to its bit location in INTFLAGSBCLR.
Both memory locations will provide the same result when read, and writing zero to any bit loca-
tion has no effect.
Bit
+0x0A/ +0x0B
Read/Write
Initial Value
Bit
+0x0C/ +0x0D
Read/Write
Initial Value
SOFIF
R/W
R
7
0
7
–
0
SUSPENDIF
R/W
R
6
0
6
–
0
RESUMEIF
R/W
R
5
0
5
–
0
RESETIF
R/W
R
4
0
4
–
0
Atmel AVR XMEGA AU
CRCIF
R/W
R
3
0
3
–
0
UNFIF
R/W
–-
R
2
0
2
0
TRNIF
OVFIF
R/W
R/W
1
0
1
0
SETUPIF
STALLIF
R/W
R/W
0
0
0
0
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