ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 292

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.3
23.3.1
8331A–AVR–07/11
Clock Generation
Internal Clock Generation - The Fractional Baud Rate Generator
The clock used for baud rate generation and for shifting and sampling data bits is generated
internally by the fractional baud rate generator or externally from the transfer clock (XCK) pin.
Five modes of clock generation are supported: normal and double-speed asynchronous mode,
master and slave synchronous mode, and master SPI mode.
Figure 23-2. Clock generation logic, block diagram.
The fractional baud rate generator is used for internal clock generation for asynchronous modes,
synchronous master mode, and master SPI mode operation. The output frequency generated
(f
peripheral clock frequency (f
baud rate (in bits per second) and for calculating the BSEL value for each mode of operation. It
also shows the maximum baud rate versus peripheral clock frequency. BSEL can be set to any
value between 0 and 4095. BSCALE can be set to any value between -7 and +7, and increases
or decreases the baud rate slightly to provide the fractional baud rate scaling of the baud rate
generator.
When BSEL is 0, BSCALE must also be 0. Also, the value 2
of the minimum number of clock cycles a frame requires. For more details, see
Rate Generation” on page
BAUD
PORT_INV
DDR_XCK
XCK
Pin
) is determined by the period setting (BSEL), an optional scale setting (BSCALE), and the
xcko
xcki
f
OSC
Baud Rate
Generator
Register
BSEL
Sync
301.
PER
).
f
Table 23-1 on page 293
BAUD
Detector
Edge
/2
Atmel AVR XMEGA AU
/4
contains equations for calculating the
ABS(BSCALE)
/2
must at most beone half
DDR_XCK
CLK2X
0
1
0
1
”Fractional Baud
0
1
1
0
UMSEL [1]
txclk
rxclk
292