ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 377

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.17.4
28.17.5
8331A–AVR–07/11
INTFLAGS – ADC Channel Interrupt Flag registers
RESH – Channel n Result register High
Table 28-17. ADC Interrupt mode
• Bits 1:0 – INTLVL[1:0]: ADC Interrupt Priority Level and Enable
These bits enable the ADC channel interrupt and select the interrupt level as described in
tion 12. ”Interrupts and Programmable Multilevel Interrupt Controller” on page
interrupt will be triggered for conditions when the IF in the INTFLAGS register is set.
• Bit 7:1 – Reserved
These bits are reserved and will always read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 0 – IF: ADC Channel Interrupt Flag
The interrupt flag is set when the ADC conversion is complete. If the channel is configured for
compare mode, the flag will be set if the compare condition is met. IF is automatically cleared
when the ADC channel interrupt vector is executed. The bit can also be cleared by writing a one
to the bit location.
For all result registers and with any ADC result resolution, a signed number is represented in 2’s
complement form and the MSB represents the sign bit.
The RESL and RESH register pair represents the 16-bit value ADCRESULT. Reading and writ-
ing 16-bit values require special attention, refer to
page 12
Bit
+0x03
Read/Write
Initial Value
12-bit, left.
12-bit, right
8-bit
INTMODE[1:0]
for details.
00
01
10
11
Bit
+0x05
Read/Write
Initial Value
R
7
–
0
COMPLETE
BELOW
ABOVE
Group Configuration
R
6
–
0
R
7
–
–
0
R
0
5
–
R
6
–
–
0
R
4
–
0
R
5
–
–
0
Interrupt mode
Conversion Complete
Compare Result Below Threshold
Reserved
Compare Result Above Threshold
Section 3.11 ”Accessing 16-bit Registers” on
Atmel AVR XMEGA AU
R
3
–
0
R
4
–
–
0
RES[11:4]
R
2
–
0
R
3
–
0
R
1
–
0
R
2
–
0
RES[11:8]
132. The enabled
R/W
IF
0
0
R
1
–
0
INTFLAGS
R
0
–
0
Sec-
377