ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 307

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.15.3
23.15.4
8331A–AVR–07/11
CTRLA – Control Register A
CTRLB – USART Control Register B
• Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 5:4 – RXCINTLVL[1:0]: Receive Complete Interrupt Level
These bits enable the receive complete interrupt and select the interrupt level, as described in
”Interrupts and Programmable Multilevel Interrupt Controller” on page
will be triggered when the RXCIF flag in the STATUS register is set.
• Bit 3:2 – TXCINTLVL[1:0]: Transmit Complete Interrupt Level
These bits enable the transmit complete interrupt and select the interrupt level, as described in
”Interrupts and Programmable Multilevel Interrupt Controller” on page
will be triggered when the TXCIF flag in the STATUS register is set.
• Bit 1:0 – DREINTLVL[1:0]: Data Register Empty Interrupt Level
These bits enable the data register empty interrupt and select the interrupt level, as described in
”Interrupts and Programmable Multilevel Interrupt Controller” on page
will be triggered when the DREIF flag in the STATUS register is set.
• Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4 – RXEN: Receiver Enable
Setting this bit enables the USART receiver. The receiver will override normal port operation for
the RxD pin, when enabled. Disabling the receiver will flush the receive buffer, invalidating the
FERR, BUFOVF, and PERR flags.
• Bit 3 – TXEN: Transmitter Enable
Setting this bit enables the USART transmitter. The transmitter will override normal port opera-
tion for the TxD pin, when enabled. Disabling the transmitter (writing TXEN to zero) will not
become effective until ongoing and pending transmissions are completed; i.e., when the transmit
Bit
+0x03
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
R
R
7
–
0
7
–
0
R
R
6
–
0
6
–
0
R/W
R
5
RXCINTLVL[1:0]
0
5
–
0
RXEN
R/W
R/W
4
0
4
0
TXEN
R/W
R/W
Atmel AVR XMEGA AU
3
TXCINTLVL[1:0]
0
3
0
CLK2X
R/W
R/W
2
0
2
0
132. The enabled interrupt
132. The enabled interrupt
132. The enabled interrupt
MPCM
R/W
R/W
1
DREINTLVL[1:0]
0
1
0
TXB8
R/W
R/W
0
0
0
0
CTRLA
CTRLB
307