ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 346

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

27.10.5
8331A–AVR–07/11
SDRAMCTRLB – SDRAM Control Register B
• Bit 13:0 – INITDLY[13:0]: SDRAM Initialization Delay
This register is used to delay the initialisation sequence after the controller is enabled until all
voltages are stabilized and the SDRAM clock has been running long enough to take the SDRAM
chip through its initialisation sequence. The initialisation sequence includes pre-charge all banks
to their idle state issuing an auto-refresh cycle and then loading the mode register. The setting in
this register is as a number of Clk
• Bit 7:6 – MRDLY[1:0]: SDRAM Mode Register Delay
These bits select the delay between LOAD MODE command and an ACTIVE command in num-
ber of Clk
Table 27-15. SDRAM Load Mode to Active delays settings
• Bit 5:3 – ROWCYCDLY[2:0]: SDRAM Row Cycle Delay
These bits select the delay between a REFRESH and an ACTIVE command in number of
Clk
Table 27-16. SDRAM Row Cycle Delay settings
• Bit 2:0 – RPDLY[2:0]: SDRAM Row to Precharge Delay
RPDLY defines the delay between an ACTIVE command and a PRECHARGE command in
number of Clk
Bit
+0x08
Read/Write
Initial Value
PER2
ROWCYDLY[2:0]
MRDLY[1:0]
cycles, according to
PER2
000
001
010
011
100
101
110
111
00
01
10
11
R/W
PER2
cycles, according to
7
0
MRDLY[1:0]
cycles, according to
R/W
6
0
Group Configuration
0CLK
1CLK
2CLK
3CLK
Group Configuration
0CLK
1CLK
2CLK
3CLK
4CLK
5CLK
6CLK
7CLK
Table 27-16 on page
R/W
5
0
PER2
ROWCYCDLY[2:0]
Table 27-15 on page
cycles.
R/W
Table 27-17 on page
4
0
Description
0 Clk
1 Clk
2 Clk
3 Clk
Description
0 Clk
1 Clk
2 Clk
3 Clk
4 Clk
5 Clk
6 Clk
7 Clk
R/W
3
0
346.
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
Atmel AVR XMEGA AU
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
346.
R/W
2
0
347.
RPDLY[2:0]
R/W
1
0
R/W
0
0
SDRAMCTRLB
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