ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 368

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ATxmega256A3BU

Manufacturer Part Number
ATxmega256A3BU
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega256A3BU

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
49
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
8
Twi (i2c)
2
Uart
6
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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28.16.3
28.16.4
8331A–AVR–07/11
REFCTRL – Reference Control register
EVCTRL – Event Control Register
• Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bits 6:4 – REFSEL[2:0]: ADC Reference Selection
These bits selects the reference for the ADC according to
Table 28-5.
• Bit 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1 – BANDGAP: Bandgap enable
Setting this bit enables the Bandgap for ADC measurement. Note that if any other functions are
using the Bandgap already, this bit does not need to be set when the internal 1.00V reference is
used in ADC or DAC, or if the Brown-out Detector is enabled.
• Bit 0 – TEMPREF: Temperature Reference enable
Setting this bit enables the temperature reference for ADC measurement.
• Bit 7:6 – SWEEP[1:0]: ADC Channel Sweep
These bits control which ADC channels are included in a channel sweep triggered by the event
system, or in free running mode. See
Bit
+0x02
Read/Write
Initial Value
Bit
+0x03
Read/Write
Initial Value
REFSEL[2:0]
101 - 111
000
001
010
011
100
R/W
R
7
0
7
0
ADC Reference selection
SWEEP[1:0]
R/W
R/W
6
0
6
0
Group Configuration
INT1V
INTVCC
AREFA
AREFB
INTVCC2
REFSEL[2:0]
R/W
R/W
5
0
5
0
Table 28-6 on page
EVSEL[2:0]
R/W
R/W
4
0
4
0
Description
10/11 of Bandgap (1.0V)
VCC/1.6
External reference from AREF pin on PORT A
External reference from AREF pin on PORT B
VCC/2
Reserved
R/W
Atmel AVR XMEGA AU
R
3
0
3
0
369.
Table 28-5 on page
R/W
R
2
0
2
0
BANDGAP
EVACT[2:0]
R/W
R/W
1
0
1
0
TEMPREF
368.
R/W
R/W
0
0
0
0
REFCTRL
EVCTRL
368

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