ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 327

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.7
26.7.1
8331A–AVR–07/11
Register Description
CTRL – Control Register
• Bit 7:6 – RESET[1:0]: CRC Reset
These bits are used to reset the CRC module, and they will always be read as zero. The CRC
registers will be reset one peripheral clock cycle after the RESET[1] bit is set.
Table 26-1.
• Bit 5 – CRC32: CRC-32 Enable
Setting this bit will enable CRC-32 instead of the default CRC-16. It cannot be changed while the
BUSY flag is set.
• Bit 4 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 3:0 – SOURCE[3:0]: Input Source
These bits select the input source for generating the CRC. The selected source is locked until
either the CRC generation is completed or the CRC module is reset. CRC generation complete
is generated and signaled from the selected source when used with the DMA controller or flash
memory.
Table 26-2.
Bit
+0x00
Read/Write
Initial Value
SOURCE[3:0]
RESET[1:0]
0000
0001
0010
0011
0100
0101
00
01
10
11
R/W
CRC reset.
CRC source
7
0
RESET[1:0]
Group configuration
NO
—
RESET0
RESET1
Group configuration
DISABLE
IO
FLASH
—
DMACH0
DMACH1
R/W
6
0
select.
CRC32
R
5
0
Description
No reset
Reserved
Reset CRC with CHECKSUM to all zeros
Reset CRC with CHECKSUM to all ones
Description
CRC disabled
I/O interface
Flash
Reserved for future use
DMA controller channel 0
DMA controller channel 1
R
4
–
0
R/W
Atmel AVR XMEGA AU
3
0
R/W
2
0
SOURCE[3:0]
R/W
1
0
R/W
0
0
CTRL
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