ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 34

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.16.6
8331A–AVR–07/11
LOCKBITS – Nonolatile Memory Lock Bit Register
• Bit 7:6 – BLBB[1:0]: Boot Lock Bit Boot Loader Section
These lock bits control the security level for the boot loader section. The BLBB bits can only be
written to a more strict locking. Resetting the BLBB bits is possible by executing a chip erase
command.
Table 4-9.
• Bit 5:4 – BLBA[1:0]: Boot Lock Bit Application Section
These lock bits control the security level for the application section. The BLBA bits can only be
written to a more strict locking. Resetting the BLBA bits is possible by executing a chip erase
command.
Bit
+0x07
Read/Write
Initial Value
BLBB[1:0]
11
10
01
00
Boot lock bit for the boot loader section.
R/W
7
1
BLBB[1:0]
Group Configuration
R/W
6
1
RWLOCK
NOLOCK
WLOCK
RLOCK
R/W
5
1
BLBA[1:0]
R/W
4
1
Description
No lock – no restrictions for SPM and (E)LPM accessing
the boot loader section.
Write lock – SPM is not allowed to write the boot loader
section.
Read lock – (E)LPM executing from the application
section is not allowed to read from the boot loader
section.
If the interrupt vectors are placed in the application
section, interrupts are disabled while executing from the
boot loader section.
Read and write lock – SPM is not allowed to write to the
boot loader section, and (E)LPM executing from the
application section is not allowed to read from the boot
loader section.
If the interrupt vectors are placed in the application
section, interrupts are disabled while executing from the
boot loader section.
R/W
Atmel AVR XMEGA AU
3
1
BLBAT[1:0]
R/W
2
1
R/W
1
1
LB[1:0]
R/W
0
1
LOCKBITS
34