ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 293

no-image

ATxmega256A3BU

Manufacturer Part Number
ATxmega256A3BU
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega256A3BU

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
49
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
8
Twi (i2c)
2
Uart
6
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATxmega256A3BU-AU
Manufacturer:
ST
Quantity:
12 000
Part Number:
ATxmega256A3BU-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATxmega256A3BU-MH
Manufacturer:
AAT
Quantity:
400
Table 23-1.
Note:
23.3.2
8331A–AVR–07/11
Operating Mode
Asynchronous normal
speed mode (CLK2X = 0)
Asynchronous double
speed mode (CLK2X = 1)
Synchronous and master
SPI mode
1. The baud rate is defined to be the transfer rate in bits per second (bps)
External Clock
Equations for calculating baud rate register settings.
For BSEL=0, all baud rates be achieved by changing BSEL instead of setting BSCALE:
BSEL = (2
External clock (XCK) is used in synchronous slave mode operation. The XCK clock input is sam-
pled on the peripheral clock frequency (f
limited by the following:
For each high and low period, XCK clock cycles must be sampled twice by the peripheral clock.
If the XCK clock has jitter, or if the high/low period duty cycle is not 50/50, the maximum XCK
clock speed must be reduced accordingly.
f
XCK
Conditions
BSCALE ≥ 0
BSCALE < 0
BSCALE ≥ 0
BSCALE < 0
f
f
f
f
f
BAUD
BAUD
BAUD
BAUD
BAUD
<
BSCALE
f
---------- -
PER
4
<
f
---------- -
f
---------- -
f
---------- -
f
---------- -
f
---------- -
1
2
3
4
5
6
7
PER
PER
PER
PER
PER
16
16
8
8
2
BSCALE-1
)
BSEL
f
f
BAUD
BAUD
f
f
BAUD
0
0
0
0
0
0
0
BAUD
Baud Rate
=
=
f
=
BAUD
=
------------------------------------------------------------------ -
16((2
--------------------------------------------------------------- -
8((2
-------------------------------------------------------------- -
2
------------------------------------------------------------- -
2
BSCALE
BSCALE
BSCALE
=
PER
BSCALE
(1)
------------------------------------ -
2
Calculation
), and the maximum XCK clock frequency (f
f
(
f
PER
f
8
BSEL
f
PER
16(
PER
PER
f
PER
BSEL )
(
BSEL )
BSEL
BSEL
Atmel AVR XMEGA AU
+
1
BSCALE
+
)
+
+
+
1)
1
1)
1)
0
0
0
0
0
0
0
)
BSEL
BSEL
BSEL
BSEL
BSEL Value Calculation
BSEL
=
=
=
BSEL
1
3
7
15
31
63
127
=
---------------------
2
------------------------------------------------ 1
2
---------------------
2
-------------------------------------------- - 1
2
BSCALE
BSCALE
BSCALE
BSCALE
1
=
1
------------------ - 1
2f
f
f
f
BAUD
PER
PER
PER
--------------------- - 1
16f
⋅ f
16
------------------ - 1
8f
8
f
f
BAUD
PER
PER
f
BAUD
BAUD
BAUD
XCK
293
)is

Related parts for ATxmega256A3BU