ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 290

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23. USART
23.1
23.2
8331A–AVR–07/11
Features
Overview
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The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast
and flexible serial communication module. The USART supports full-duplex communication and
asynchronous and synchronous operation. The USART can be set in SPI master mode and
used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide
range of standards. The USART is buffered in both directions, enabling continued data transmis-
sion without any delay between frames. Separate interrupts for receive and transmit complete
enable fully interrupt driven communication. Frame error and buffer overflow are detected in
hardware and indicated with separate status flags. Even or odd parity generation and parity
check can also be enabled.
A block diagram of the USART is shown in
are the clock generator, the transmitter, and the receiver, which are indicated in dashed boxes.
Full-duplex operation
Asynchronous or synchronous operation
Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
Fractional baud rate generator
Built-in error detection and correction schemes
Separate interrupts for
Multiprocessor communication mode
Master SPI mode
IRCOM module for IrDA compliant pulse modulation/demodulation
– Synchronous clock rates up to 1/2 of the device clock frequency
– Asynchronous clock rates up to 1/8 of the device clock frequency
– Can generate desired baud rate from any system clock frequency
– No need for external oscillator with certain frequencies
– Odd or even parity generation and parity check
– Data overrun and framing error detection
– Noise filtering includes false start bit detection and digital low-pass filter
– Transmit complete
– Transmit data register empty
– Receive complete
– Addressing scheme to address a specific devices on a multidevice bus
– Enable unaddressed devices to automatically ignore all frames
– Double buffered operation
– Configurable data order
– Operation up to 1/2 of the peripheral clock frequency
Figure 23-1 on page
Atmel AVR XMEGA AU
291. The main functionalblocks
290