ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 328

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.7.2
26.7.3
26.7.4
8331A–AVR–07/11
STATUS – Status Register
DATAIN – CRC Data Input Register
CHECKSUM0 – Checksum Byte 0
Table 26-2.
• Bit 7:2 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 1 – ZERO: Checksum Zero
This flag is set if the CHECKSUM is zero when the CRC generation is complete. It is automati-
cally cleared when a new CRC source is selected.
When running CRC-32 and adding the checksum at the end of the packet (as little endian), one
should end up with the "magic value" 0x2144df1c, and not zero. To still get zero, append the
non-bit reversed and non-complemented value.
See the description of CHECKSUM to read out different versions of the CHECKSUM.
• Bit 0 – BUSY: Busy
This flag is read as one when a source configuration is selected and as long as the source is
using the CRC module. If the I/O interface is selected as the source, the flag can be cleared by
writing a one this location. If a DMA channel if selected as the source, the flag is cleared when
the DMA channel transaction is completed or aborted. If flash memory is selected as the source,
the flag is cleared when the CRC generation is completed.
• Bit 7:0 – DATAIN[7:0]
This register is used to store the data for which the CRC checksum is computed. A new CHECK-
SUM is ready one clock cycle after the DATAIN register is written.
CHECKSUM0, CHECKSUM1, CHECKSUM2, and CHECKSUM3 represent the 16- or 32-bit
CHECKSUM value and the generated CRC. The registers are reset to zero by default, but it is
Bit
+0x03
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
SOURCE[3:0]
0110
0111
1xxx
W
CRC source
7
0
7
–
R
0
Group configuration
DMACH2
DMACH3
—
W
R
6
0
6
–
0
select.
W
R
5
0
5
–
0
Description
DMA controller channel 2
DMA controller channel 3
Reserved for future use
W
R
4
0
4
–
0
DATAIN[7:0]
Atmel AVR XMEGA AU
W
R
3
0
3
–
0
W
2
–
R
0
2
0
ZERO
W
R
1
0
1
0
BUSY
R/W
W
0
0
0
0
STATUS
DATAIN
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