SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 1049

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

39.6.7
Figure 39-2. Conversion Sequence
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Write DACC_CDR
Selected Channel
Write USER_SEL
Read DACC_ISR
DAC Channel 0
DAC Channel 1
Output
Output
field
TXRDY
MCK
EOC
DACC Timings
None
Select Channel 0
The DACC startup time must be defined by the user in the STARTUP field of the
Register.
This startup time differs depending of the use of the fast wake-up mode along with sleep mode,
in this case the user must set the STARTUP time corresponding to the fast wake up and not the
standard startup time.
A max speed mode is available by setting the MAXS bit to 1 in the DACC_MR register. Using
this mode, the DAC Controller no longer waits to sample the end of cycle signal coming from the
DACC block to start the next conversion and uses an internal counter instead. This mode gains
2 DACC Clock periods between each consecutive conversion.
Warning: Using this mode, the EOC interrupt of the DACC_IER register should not be used as it
is 2 DACC Clock periods late.
After 20 µs the analog voltage resulting from the converted data will start decreasing, therefore it
is necessary to refresh the channel on a regular basis to prevent this voltage loss. This is the
purpose of the REFRESH field in the DACC Mode Register where the user will define the period
for the analog channels to be refreshed.
Warning: A REFRESH PERIOD field set to 0 will disable the refresh function of the DACC
channels.
Data 0 Data 1
Channel 0
Data 0
Select Channel 1
Data 2
CDR FIFO not full
Data 1
Channel 1
SAM3S8/SD8
SAM3S8/SD8
DACC Mode
Data 2
1049
1049