SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 61

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

10.4.6.1
10.4.7
10.4.7.1
10.4.7.2
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Synchronization primitives
Little-endian format
A Load-Exclusive instruction
A Store-Exclusive instruction
In little-endian format, the processor stores the least significant byte of a word at the lowest-
numbered byte, and the most significant byte at the highest-numbered byte. For example:
The Cortex-M3 instruction set includes pairs of synchronization primitives. These provide a non-
blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. Software can use them to perform a guaranteed read-modify-write memory update
sequence, or for a semaphore mechanism.
A pair of synchronization primitives comprises:
Used to read the value of a memory location, requesting exclusive access to that location.
Used to attempt to write to the same memory location, returning a status bit to a register. If this
bit is:
0: it indicates that the thread or process gained exclusive access to the memory, and the write
succeeds,
1: it indicates that the thread or process did not gain exclusive access to the memory, and no
write is performed,
The pairs of Load-Exclusive and Store-Exclusive instructions are:
Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive
instruction.
To perform a guaranteed read-modify-write of a memory location, software must:
• the word instructions LDREX and STREX
• the halfword instructions LDREXH and STREXH
• the byte instructions LDREXB and STREXB.
• Use a Load-Exclusive instruction to read the value of the location.
• Update the value, as required.
• Use a Store-Exclusive instruction to attempt to write the new value back to the memory
Address A
location, and tests the returned status bit. If this bit is:
0: The read-modify-write completed successfully,
A+1
A+2
A+3
7
Memory
B0
B1
B2
B3
0
lsbyte
msbyte
31
B3
24 23
B2
Register
16 15
B1
8 7
B0
0
SAM3S8/SD8
SAM3S8/SD8
61
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