SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 520

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

Table 27-4.
Notes:
Note:
520
520
Offset
0x150
0x154
0x158
0x15C
0x160
0x164
0x0168
to
0x018C
1. Reset value depends on the product implementation.
2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO
4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have
if an offset is not listed in the table it must be considered as reserved.
SAM3S8/SD8
SAM3S8/SD8
Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
occurred.
Register
Parallel Capture Mode Register
Parallel Capture Interrupt Enable Register
Parallel Capture Interrupt Disable Register
Parallel Capture Interrupt Mask Register
Parallel Capture Interrupt Status Register
Parallel Capture Reception Holding Register
Reserved for PDC Registers
Register Mapping (Continued)
Name
PIO_PCMR
PIO_PCIMR
PIO_PCRHR
PIO_PCIER
PIO_PCIDR
PIO_PCISR
Read-write
Read-only
Read-only
Read-only
Write-only
Write-only
Access
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
0x00000000
0x00000000
0x00000000
0x00000000
Reset
–
–