SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 954

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

36.3
Figure 36-1. Block Diagram
36.3.1
954
954
MCK
UDPCK
udp_int
Block Diagram
SAM3S8/SD8
SAM3S8/SD8
Atmel Bridge
MCU
APB
Signal Description
Bus
to
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by
reading and writing 8-bit values to APB registers.
The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain
(MCK) and a 48 MHz clock (UDPCK) used by the 12 MHz domain.
A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE).
The signal external_resume is optional. It allows the UDP peripheral to wake up once in system
mode. The host is then notified that the device asks for a resume. This optional feature must
also be negotiated with the host during the enumeration.
Table 36-2.
Signal Name
UDPCK
MCK
udp_int
DDP
DDM
U
e
n
e
a
e
s
c
r
I
t
r
f
Signal Names
W
a
p
p
e
Master Clock
Domain
r
r
USB Device
RAM
FIFO
Dual
Port
Description
48 MHz clock
Master clock
Interrupt line connected to the Interrupt Controller
USB D+ line
USB D- line
Recovered 12 MHz
Domain
W
a
p
p
e
r
r
Suspend/Resume Logic
12 MHz
Interface
Engine
Serial
SIE
txoen
eopn
txd
rxdm
rxd
rxdp
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Type
input
input
input
I/O
I/O
Transceiver
Embedded
USB
DDM
DDP