SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 576
SAM3SD8B
Manufacturer Part Number
SAM3SD8B
Description
Manufacturer
Atmel Corporation
- Current page: 576 of 1143
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28.9.2
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• DIV: Clock Divider
0 = The Clock Divider is not active.
Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The
minimum bit rate is MCK/2 x 4095 = MCK/8190.
576
576
31
23
15
–
–
–
7
SAM3S8/SD8
SAM3S8/SD8
SSC Clock Mode Register
30
22
14
SSC_CMR
0x40004004
Read-write
–
–
–
6
29
21
13
–
–
–
5
28
20
12
–
–
–
4
DIV
“SSC Write Protect Mode Register”
27
19
11
–
–
3
26
18
10
–
–
2
DIV
.
25
17
–
–
9
1
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
24
16
–
–
8
0
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