SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 885

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

35.6.2.6
Figure 35-9. Fault Protection
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
fault input 0
fault input 1
fault input y
Fault Protection
Glitch
Filter
Glitch
Filter
FFIL0
FFIL1
0
1
0
1
6 inputs provide fault protection which can force any of the PWM output pair to a programmable
value. This mechanism has priority over output overriding.
The polarity level of the fault inputs is configured by the FPOL field in the
Register”
Counter, to name but a few, the polarity level must be FPOL = 1. For fault inputs coming from
external GPIO pins the polarity level depends on the user's implementation.
The configuration of the Fault Activation Mode (FMOD bit in PWMC_FMR) depends on the
peripheral generating the fault. If the corresponding peripheral does not have “Fault Clear” man-
agement, then the FMOD configuration to use must be FMOD = 1, to avoid spurious fault
detection. Check the corresponding peripheral documentation for details on handling fault
generation.
The fault inputs can be glitch filtered or not in function of the FFIL field in the PWM_FMR regis-
ter. When the filter is activated, glitches on fault inputs with a width inferior to the PWM master
clock (MCK) period are rejected.
A fault becomes active as soon as its corresponding fault input has a transition to the pro-
grammed polarity level. If the corresponding bit FMOD is set to 0 in the PWM_FMR register, the
fault remains active as long as the fault input is at this polarity level. If the corresponding FMOD
bit is set to 1, the fault remains active until the fault input is not at this polarity level anymore and
until it is cleared by writing the corresponding bit FCLR in the
(PWM_FSCR). By reading the
current level of the fault inputs by means of the field FIV, and can know which fault is currently
active thanks to the FS field.
Each fault can be taken into account or not by the fault protection mechanism in each channel.
To be taken into account in the channel x, the fault y must be enabled by the bit FPEx[y] in the
“PWM Fault Protection Enable Registers” (PWM_FPE1). However the synchronous channels
(see
of the channel 0 (bits FPE0[y]).
The fault protection on a channel is triggered when this channel is enabled and when any one of
the faults that are enabled for this channel is active. It can be triggered even if the PWM master
clock (MCK) is not running but only by a fault input that is not glitch filtered.
FIV0
FIV1
Section 35.6.2.7 “Synchronous
FPOL0
FPOL1
=
=
(PWM_FMR). For fault inputs coming from internal peripherals such as ADC, Timer
FMOD0
FMOD1
Write FCLR0 at 1
Write FCLR1 at 1
SET
CLR
SET
CLR
OUT
OUT
“PWM Fault Status Register”
FMOD0
FMOD1
Channels”) do not use their own fault enable bits, but those
0
1
0
1
Fault 0 Status
FS0
Fault 1 Status
FS1
FPEx[1]
FPEx[0]
FPE0[1]
FPE0[0]
SYNCx
SYNCx
0
1
0
1
(PWM_FSR), the user can read the
from fault 0
from fault 1
from fault y
“PWM Fault Clear Register”
SAM3S8/SD8
SAM3S8/SD8
From Output
From Output
Override
Override
FPVHx
FPVLx
OOHx
OOLx
“PWM Fault Mode
Fault protection
channel x
on PWM
0
1
1
0
PWMHx
PWMLx
885
885