SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 892

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

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Method 3: Automatic write of duty-cycle values and automatic trigger of the update
SAM3S8/SD8
SAM3S8/SD8
In this mode, the update of the duty cycle values is made automatically by the Peripheral DMA
Controller (PDC). The update of the period value, the dead-time values and the update period
value must be done by writing in their respective update registers with the CPU (respectively
PWM_CPRDUPDx, PWM_DTUPDx and PWM_SCUPUPD).
To trigger the update of the period value and the dead-time values, the user must use the bit
UPDULOCK which allows to update synchronously (at the same PWM period) the synchronous
channels:
After writing the UPDULOCK bit to 1, it is held at this value until the update occurs, then it is read
0.
The update of the duty-cycle values and the update period value is triggered automatically after
an update period.
To configure the automatic update, the user must define a value for the Update Period by the
field UPR in the
troller waits UPR+1 periods of synchronous channels before updating automatically the duty
values and the update period value.
Using the PDC removes processor overhead by reducing its intervention during the transfer.
This significantly reduces the number of clock cycles required for a data transfer, which
improves microcontroller performance.
The PDC must write the duty-cycle values in the synchronous channels index order. For exam-
ple if the channels 0, 1 and 3 are synchronous channels, the PDC must write the duty-cycle of
the channel 0 first, then the duty-cycle of the channel 1, and finally the duty-cycle of the channel
3.
The status of the PDC transfer is reported in the
(PWM_ISR2) by the following flags:
Depending on the interrupt mask in the PWM_IMR2 register, an interrupt can be generated by
these flags.
• If the bit UPDULOCK is set to 1, the update is done at the next PWM period of the
• If the UPDULOCK bit is not set to 1, the update is locked and cannot be performed.
• WRDY: this flag is set to 1 when the PWM Controller is ready to receive new duty-cycle
• ENDTX: this flag is set to 1 when a PDC transfer is completed
• TXBUFE: this flag is set to 1 when the PDC buffer is empty (no pending PDC transfers)
• UNRE: this flag is set to 1 when the update period defined by the UPR field has elapsed
synchronous channels.
values and a new update period value. It is reset to 0 when the PWM_ISR2 register is read.
The user can choose to synchronize the WRDY flag and the PDC transfer request with a
comparison match (see
PTRCS in the PWM_SCM register.
while the whole data has not been written by the PDC. It is reset to 0 when the PWM_ISR2
register is read.
“PWM Sync Channels Update Period Register”
Section 35.6.3 “PWM Comparison
“PWM Interrupt Status Register 2”
Units”), by the fields PTRM and
(PWM_SCUP). The PWM con-
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12