SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1082

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

39.5.2.3
39.5.2.4
39.5.2.5
1082
1082
SAM3X/A
SAM3X/A
USB Reset
Endpoint Reset
Endpoint Activation
The USB bus reset is managed by hardware. It is initiated by a connected host.
When a USB reset is detected on the USB line, the following operations are performed by the
controller:
A n e n d p o i n t c a n b e r e s e t a t a n y t i m e b y w r i t i n g a o n e t o t h e E n d p o i n t x R e s e t
(UOTGHS_DEVEPT.EPRSTx) bit. This is recommended before using an endpoint upon hard-
ware reset or when a USB bus reset has been received. This resets:
Note:
The endpoint configuration remains active and the endpoint is still enabled.
The endpoint reset may be associated with a clear of the data toggle sequence as an answer to
the CLEAR_FEATURE USB request. This can be achieved by writing a one to the Reset Data
Toggle Set bit in the Endpoint x Control Set register (UOTGHS_DEVEPTIERx.RSTDTS) (this
will set the Reset Data Toggle (UOTGHS_DEVEPTIMRx.RSTDT) bit).
In the end, the user has to write a zero to the UOTGHS_DEVEPT.EPRSTx bit to complete the
reset operation and to start using the FIFO.
The endpoint is maintained inactive and reset (see
it is disabled (UOTGHS_DEVEPT.EPENx is written to zero). UOTGHS_DEVEPTISRx.DTSEQ
is also reset.
The algorithm represented on
an endpoint.
• All endpoints are disabled, except the default control endpoint.
• The default control endpoint is reset (see
• The data toggle sequence of the default control endpoint is cleared.
• At the end of the reset process, the End of Reset (UOTGHS_DEVISR.EORST) bit is set.
• During a reset, the UOTGHS automatically switches to the Hi-Speed mode if the host is Hi-
• the internal state machine of this endpoint,
• the receive and transmit bank FIFO counters,
• all registers of this endpoint (UOTGHS_DEVEPTCFGx, UOTGHS_DEVEPTISRx, the
Speed capable (the reset is called Hi-Speed reset). The user should observe the
UOTGHS_SR.SPEED field to know the speed running at the end of the reset
(UOTGHS_DEVISR.EORST is one).
Endpoint x Control (UOTGHS_DEVEPTIMRx) register), except its configuration
(UOTGHS_DEVEPTCFGx.ALLOC, UOTGHS_DEVEPTCFGx.EPBK,
UOTGHS_DEVEPTCFGx.EPSIZE, UOTGHS_DEVEPTCFGx.EPDIR,
UOTGHS_DEVEPTCFGx.EPTYPE) and the Data Toggle Sequence
(UOTGHS_DEVEPTISRx.DTSEQ) field.
The interrupt sources located in the UOTGHS_DEVEPTISRx register are not cleared when a USB
bus reset has been received.
Figure 39-13 on page 1083
Section 39.5.2.4
Section 39.5.2.4
must be followed in order to activate
for more details).
for more details) as long as
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12