SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 68

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

11.5.1
11.5.1.1
11.5.1.2
11.5.1.3
11.5.1.4
11.5.1.5
11.5.2
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SAM3X/A
SAM3X/A
Memory regions, types and attributes
Memory system ordering of memory accesses
Normal
Device
Strongly-ordered
Shareable
Execute Never (XN)
The memory map and the programming of the MPU split the memory map into regions. Each
region has a defined memory type, and some regions have additional memory attributes. The
memory type and attributes determine the behavior of accesses to the region.
The memory types are:
The processor can re-order transactions for efficiency, or perform speculative reads.
The processor preserves transaction order relative to other transactions to Device or Strongly-
ordered memory.
The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly-ordered memory mean that the
memory system can buffer a write to Device memory, but must not buffer a write to Strongly-
ordered memory.
The additional memory attributes include.
For a shareable memory region, the memory system provides data synchronization between
bus masters in a system with multiple bus masters, for example, a processor with a DMA
controller.
Strongly-ordered memory is always shareable.
If multiple bus masters can access a non-shareable memory region, software must ensure data
coherency between the bus masters.
Means the processor prevents instruction accesses. Any attempt to fetch an instruction from an
XN region causes a memory management fault exception.
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing this does not affect the behavior of the instruction sequence. Nor-
mally, if correct program execution depends on two memory accesses completing in program
order, software must insert a memory barrier instruction between the memory access instruc-
tions, see
“Software ordering of memory accesses” on page
70.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12