SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 349

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

23.3
Figure 23-1. DMA Controller (DMAC) Block Diagram
23.4
23.4.1
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Block Diagram
Functional Description
Datapath Bundles
Basic Definitions
DMA Read
DMA FIFO Controller
Up to 64 bytes
DMA FIFO
DMA Global Control
DMA Channel 0
and Data Mux
DMA Channel 0
Write data path
to destination
DMA Channel 0
Read data path
from source
Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then
stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form
a channel.
Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previ-
ously read from the source peripheral).
Memory: Source or destination that is always “ready” for a DMAC transfer and does not require
a handshaking interface to interact with the DMAC.
Programmable Arbitration Policy: Modified Round Robin and Fixed Priority are available by
means of the ARB_CFG bit in the Global Configuration Register (DMAC_GCFG). The fixed pri-
DMA Channel 1
DMA Channel 2
DMA AHB Lite Master Interface 0
DMA Channel n
DMA Destination
Control State Machine
Destination Pointer
Management
DMA Source
Control State Machine
Source Pointer
Management
AMBA AHB Layer 0
DMA Destination
Request Arbiter
DMA Global
Requests Pool
DMA Source
Atmel APB rev2 Interface
Trigger Manager
External
Triggers
Soft
Triggers
Status
Registers
Configuration
Registers
DMA Interrupt
Controller
DMA
REQ/ACK
Interface
SAM3X/A
SAM3X/A
DMA
Hardware
Handshaking
Interface
DMA
Atmel
APB
Interface
DMA Interrupt
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