SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 331

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

22. Bus Matrix (MATRIX)
22.1
22.2
22.2.1
22.2.2
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Description
Embedded Characteristics
Matrix Masters
Matrix Slaves
Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel
access paths between multiple AHB masters and slaves in a system, which increases the over-
all bandwidth. Bus Matrix interconnects 6 AHB Masters to 9 AHB Slaves. The normal latency to
connect a master to a slave is one cycle except for the default master of the accessed slave
which is connected directly (zero cycle latency).
The Bus Matrix user interface is compliant with
vides a Chip Configuration User Interface with Registers that allow the Bus Matrix to support
application specific features.
The Bus Matrix of the SAM3A/X series product manages 5 (SAM3A) or 6
which means that each master can perform an access concurrently with others, to an available
slave.
Each master has its own decoder, which is defined specifically for each master. In order to sim-
plify the addressing, all the masters have the same decoding.
Table 22-1.
The Bus Matrix of the SAM3A/X series product manages 9 slaves. Each slave has its own arbi-
ter, allowing a different arbitration per slave.
Table 22-2.
Master 0
Master 1
Master 2
Master 3
Master 4
Master 5
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
Slave 5
Slave 6
Slave 7
Slave 8
List of Bus Matrix Masters
List of Bus Matrix Slaves
Internal SRAM0
Internal SRAM1
Internal ROM
Internal Flash
USB High Speed Dual Port RAM (DPR)
Nand Flash Controller RAM
External Bus Interface
High Speed Peripheral Bridge
Low Speed Peripheral Bridge
Cortex-M3 Instruction/Data
Cortex-M3 System
Peripheral DMA Controller (PDC)
USB OTG High Speed DMA
DMA Controller
Ethernet MAC (AT91SAM3X)
the ARM A
dvance Peripheral Bus (APB) and pro-
(
SAM3X
SAM3X/A
SAM3X/A
)
masters,
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