SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 403

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

25. AHB SDRAM Controller (SDRAMC)
25.1
25.2
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Description
Embedded Characteristics
The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the
interface to an external 16-bit DRAM device. The page size supports ranges from 2048 to 8192
and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word
(32-bit) accesses.
The SDRAM Controller supports a read or write burst length of one location. It keeps track of the
active row in each bank, thus maximizing SDRAM performance, e.g., the application may be
placed in one bank and data in the other banks. So as to optimize performance, it is advisable to
avoid accessing different rows in the same bank.
The SDRAM controller supports a CAS latency of 1, 2 or 3 and optimizes the read access
depending on the frequency.
The different modes available - self-refresh, power-down and deep power-down modes - mini-
mize power consumption on the SDRAM device.
• Numerous Configurations Supported
• Programming Facilities
• Energy-saving Capabilities
• Error Detection
• SDRAM Power-up Initialization by Software
• CAS Latency of 1, 2, 3 Supported
• Auto Precharge Command Not Used
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with Two or Four Internal Banks
– SDRAM with 16-bit Data Path
– Word, Half-word, Byte Access
– Automatic Page Break When Memory Boundary Has Been Reached
– Multibank Ping-pong Access
– Timing Parameters Specified by Software
– Automatic Refresh Operation, Refresh Rate is Programmable
– Automatic Update of DS, TCR and PASR Parameters (Mobile SDRAM Devices)
– Self-refresh, Power-down and Deep Power Modes Supported
– Supports Mobile SDRAM Devices
– Refresh Error Interrupt
SAM3X/A
SAM3X/A
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