SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 995

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

38.6.2.6
Figure 38-9. Fault Protection
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
fault input 0
fault input 1
fault input y
Fault Protection
Glitch
Filter
Glitch
Filter
FFIL0
FFIL1
0
1
0
1
By using buffer registers PWM_OSSUPD and PWM_OSCUPD, the output selection of PWM
outputs is done synchronously to the channel counter, at the beginning of the next PWM period.
By using registers PWM_OSS and PWM_OSC, the output selection of PWM outputs is done
asynchronously to the channel counter, as soon as the register is written.
The value of the current output selection can be read in PWM_OS.
While overriding PWM outputs, the channel counters continue to run, only the PWM outputs are
forced to user defined values.
6 inputs provide fault protection which can force any of the PWM output pair to a programmable
value. This mechanism has priority over output overriding.
The polarity level of the fault inputs is configured by the FPOL field in the
Register”
Counter, to name but a few, the polarity level must be FPOL = 1. For fault inputs coming from
external GPIO pins the polarity level depends on the user's implementation.
The configuration of the Fault Activation Mode (FMOD bit in PWMC_FMR) depends on the
peripheral generating the fault. If the corresponding peripheral does not have “Fault Clear” man-
agement, then the FMOD configuration to use must be FMOD = 1, to avoid spurious fault
detection. Check the corresponding peripheral documentation for details on handling fault
generation.
The fault inputs can be glitch filtered or not in function of the FFIL field in the PWM_FMR regis-
ter. When the filter is activated, glitches on fault inputs with a width inferior to the PWM master
clock (MCK) period are rejected.
A fault becomes active as soon as its corresponding fault input has a transition to the pro-
grammed polarity level. If the corresponding bit FMOD is set to 0 in the PWM_FMR register, the
fault remains active as long as the fault input is at this polarity level. If the corresponding FMOD
bit is set to 1, the fault remains active until the fault input is not at this polarity level anymore and
until it is cleared by writing the corresponding bit FCLR in the
(PWM_FSCR). By reading the
FIV0
FIV1
FPOL0
FPOL1
=
=
(PWM_FMR). For fault inputs coming from internal peripherals such as ADC, Timer
FMOD0
FMOD1
Write FCLR0 at 1
Write FCLR1 at 1
SET
CLR
SET
CLR
OUT
OUT
“PWM Fault Status Register”
FMOD0
FMOD1
0
1
0
1
Fault 0 Status
FS0
Fault 1 Status
FS1
FPEx[1]
FPEx[0]
FPE0[1]
FPE0[0]
SYNCx
SYNCx
0
1
0
1
(PWM_FSR), the user can read the
from fault 0
from fault 1
from fault y
“PWM Fault Clear Register”
From Output
From Output
Override
Override
FPVHx
FPVLx
OOHx
OOLx
“PWM Fault Mode
SAM3X/A
SAM3X/A
Fault protection
channel x
on PWM
0
1
1
0
PWMHx
PWMLx
995
995