SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 356

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

23.4.5.1
356
356
Single-buffer Transfer (Row 1)
SAM3X/A
SAM3X/A
Programming Examples
The “BTSIZE, SADDR and DADDR” columns indicate where the values of DMAC_SARx,
DMAC_DARx, DMAC_CTLx, and DMAC_LLPx are obtained for the next buffer transfer when
multi-buffer DMAC transfers are enabled.
1. Read the Channel Handler Status Register DMAC_CHSR.ENAx Field to choose a free
2. Clear any pending interrupts on the channel from the previous DMAC transfer by read-
3. Program the following channel registers:
4. After the DMAC selected channel has been programmed, enable the channel by writing
5. Source and destination request single and chunk DMAC transactions to transfer the
(disabled) channel.
ing the interrupt status register, DMAC_EBCISR.
a. Write the starting source address in the DMAC_SADDRx register for channel x.
b. Write the starting destination address in the DMAC_DADDRx register for
c. Write the next descriptor address in the DMA_DSCRx register for channel x with
d. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 1
e. Write the control information for the DMAC transfer in the DMAC_CTRLAx and
– i. Set up the transfer type (memory or non-memory peripheral for source and
– ii. Set up the transfer characteristics, such as:
f.
– i. Designate the handshaking interface type (hardware or software) for the source
– ii. If the hardware handshaking interface is activated for the source or destination
a ‘1’ to the DMAC_CHER.ENAx bit, where x is the channel number. Make sure that bit
0 of DMAC_EN.ENABLE register is enabled.
buffer of data (assuming non-memory peripherals). The DMAC acknowledges at the
completion of every transaction (chunk and single) in the buffer and carries out the buf-
fer transfer.
destination) and flow control device by programming the FC of the DMAC_CTRLBx
register.
and destination peripherals. This is not required for memory. This step requires
programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates
the hardware handshaking interface to handle source/destination requests. Writing a
‘0’ activates the software handshaking interface to handle source/destination
requests.
peripheral, assign a handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DST_PER bits, respectively.
– Transfer width for the source in the SRC_WIDTH field.
– Transfer width for the destination in the DST_WIDTH field.
– Incrementing/decrementing or fixed address for source in SRC_INC field.
– Incrementing/decrementing or fixed address for destination in DST_INC field.
channel x.
0x0..
as shown in
DMAC_CTRLBx registers for channel x. For example, in the register, you can pro-
gram the following:
Write the channel configuration information into the DMAC_CFGx register for chan-
nel x.
Table 23-4 on page
355.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12