SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1091

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

39.5.2.14
39.5.2.15
39.5.2.16
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Underflow
Overflow
HB IsoIn Error
This error only exists for isochronous IN/OUT endpoints. It sets the Underflow Interrupt
(UOTGHS_DEVEPTISRx.UNDERFI) bit, which triggers a PEP_x interrupt if the Underflow Inter-
rupt Enable (UOTGHS_DEVEPTIMRx.UNDERFE) bit is one.
T h i s e r r o r e x i s t s f o r a l l e n d p o i n t t y p e s . I t s e t s t h e O v e r f l o w i n t e r r u p t
(UOTGHS_DEVEPTISRx.OVERFI) bit, which triggers a PEP_x interrupt if the Overflow Interrupt
Enable (UOTGHS_DEVEPTIMRx.OVERFE) bit is one.
This error only exists for high-bandwidth isochronous IN endpoints.
At the end of the micro-frame, if at least one packet has been sent to the host and less banks
t h a n
UOTGHS_DEVEPTIMRx.UOTGHS_DEVEPTIMRx.FIFOCON) for this micro-frame, it sets the
UOTGHS_DEVEPTISRx.HBISOINERRORI bit, which triggers a PEP_x interrupt if the High
Bandwidth Isochronous IN Error Interrupt Enable (HBISOINERRORE) bit is one.
For instance, if the Number of Transaction per MicroFrame for Isochronous Endpoint
(NBTRANS field in UOTGHS_DEVEPTCFGx is three (three transactions per micro-frame), only
two banks are filled by the CPU (three expected) for the current micro-frame. Then, the
HBISOINERRI interrupt is generated at the end of the micro-frame. Note that an UNDERFI inter-
rupt is also generated (with an automatic zero-length-packet), except in the case of a missing IN
token.
• For a single bank, a NYET handshake is always sent to the host (on Bulk-out transaction) to
• For a double bank, the UOTGHS responds to the OUT/DATA transaction with an ACK
• An underflow can occur during the IN stage if the host attempts to read from an empty bank.
• An underflow cannot occur during the OUT stage on a CPU action, since the user may only
• An underflow can also occur during the OUT stage if the host sends a packet while the bank
• An underflow cannot occur during the IN stage on a CPU action, since the user may only
• An overflow can occur during the OUT stage if the host attempts to write into a bank which is
• An overflow cannot occur during the IN stage on a CPU action, since the user may only write
indicate that the current packet is acknowledged but there is no room for the next one.
handshake when the endpoint accepted the data successfully and has room for another data
payload (the second bank is free).
A zero-length packet is then automatically sent by the UOTGHS.
read if the bank is not empty (UOTGHS_DEVEPTISRx.RXOUTI is one or
UOTGHS_DEVEPTISRx.RWALL is one).
is already full. Typically, the CPU is not fast enough. The packet is lost.
write if the bank is not full (UOTGHS_DEVEPTISRx.TXINI is one or
UOTGHS_DEVEPTISRx.RWALL is one).
too small for the packet. The packet is acknowledged and the
UOTGHS_DEVEPTISRx.RXOUTI bit is set as if no overflow had occurred. The bank is filled
with all the first bytes of the packet that fit in.
if the bank is not full (UOTGHS_DEVEPTISRx.TXINI is one or
UOTGHS_DEVEPTISRx.RWALL is one).
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