STM32F205ZG STMicroelectronics, STM32F205ZG Datasheet

no-image

STM32F205ZG

Manufacturer Part Number
STM32F205ZG
Description
High-performance ARM Cortex-M3 MCU with 1 Mbyte Flash, 120 MHz CPU, ART Accelerator
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F205ZG

10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STM32F205ZGT6
Manufacturer:
STMicroelectronics
Quantity:
11
Part Number:
STM32F205ZGT6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STM32F205ZGT6
Manufacturer:
ST
0
Company:
Part Number:
STM32F205ZGT6,,20,LQFP-144,ST,,,,20+
0
Part Number:
STM32F205ZGTG
Manufacturer:
ST
0
USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
Features
December 2011
Core: ARM 32-bit Cortex™-M3 CPU with
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
performance from Flash memory, frequency up
to 120 MHz, memory protection unit,
150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1)
Memories
– Up to 1 Mbyte of Flash memory
– 512 bytes of OTP memory
– Up to 128 + 4 Kbytes of SRAM
– Flexible static memory controller that
– LCD parallel interface, 8080/6800 modes
Clock, reset and supply management
– From 1.65 to 3.6 V application supply and
– POR, PDR, PVD and BOR
– 4 to 26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
Low power
– Sleep, Stop and Standby modes
– V
3 × 12-bit, 0.5 µs A/D converters
– up to 24 channels
– up to 6 MSPS in triple interleaved mode
2 × 12-bit D/A converters
General-purpose DMA
– 16-stream DMA controller with centralized
Up to 17 timers
– Up to twelve 16-bit and two 32-bit timers,
Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™
supports Compact Flash, SRAM, PSRAM,
NOR and NAND memories
I/Os
accuracy at 25 °C)
registers, and optional 4 KB backup SRAM
FIFOs and burst support
up to 120 MHz, each with up to 4
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
BAT
ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM,
supply for RTC, 20 × 32 bit backup
Doc ID 15818 Rev 8
Table 1.
STM32F205xx
STM32F207xx
Reference
LQFP100 (14 × 14 mm)
LQFP176 (24 × 24 mm)
LQFP144 (20 × 20 mm)
LQFP64 (10 × 10 mm)
Up to 140 I/O ports with interrupt capability:
– Up to 136 fast I/Os up to 60 MHz
– Up to 138 5 V-tolerant I/Os
Up to 15 communication interfaces
– Up to 3 × I
– Up to 4 USARTs and 2 UARTs (7.5 Mbit/s,
– Up to 3 SPIs (30 Mbit/s), 2 with muxed I
– 2 × CAN interfaces (2.0B Active)
– SDIO interface
Advanced connectivity
– USB 2.0 full-speed device/host/OTG
– USB 2.0 high-speed/full-speed
– 10/100 Ethernet MAC with dedicated DMA:
8- to 14-bit parallel camera interface: up to
48 Mbyte/s
CRC calculation unit, 96-bit unique ID
Analog true random number generator
ISO 7816 interface, LIN, IrDA, modem
control)
to achieve audio class accuracy via audio
PLL or external PLL
controller with on-chip PHY
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
supports IEEE 1588v2 hardware, MII/RMII
Device summary
STM32F205RB, STM32F205RC, STM32F205RE,
STM32F205RF, STM32F205RG, STM32F205VB,
STM32F205VC, STM32F205VE, STM32F205VF
STM32F205VG, STM32F205ZC, STM32F205ZE,
STM32F205ZF, STM32F205ZG
STM32F207IC, STM32F207IE, STM32F207IF,
STM32F207IG, STM32F207ZC, STM32F207ZE,
STM32F207ZF, STM32F207ZG, STM32F207VC,
STM32F207VE, STM32F207VF, STM32F207VG
2
C interfaces (SMBus/PMBus)
STM32F205xx
STM32F207xx
(10 × 10 mm)
UFBGA176
Part number
FBGA
(0.400 mm pitch)
WLCSP64+2
www.st.com
FBGA
1/170
2
S
1

STM32F205ZG Summary of contents

Page 1

... Analog true random number generator Table 1. Device summary Reference STM32F205RB, STM32F205RC, STM32F205RE, STM32F205RF, STM32F205RG, STM32F205VB, STM32F205xx STM32F205VC, STM32F205VE, STM32F205VF STM32F205VG, STM32F205ZC, STM32F205ZE, STM32F205ZF, STM32F205ZG STM32F207IC, STM32F207IE, STM32F207IF, STM32F207IG, STM32F207ZC, STM32F207ZE, STM32F207xx STM32F207ZF, STM32F207ZG, STM32F207VC, STM32F207VE, STM32F207VF, STM32F207VG Doc ID 15818 Rev 8 STM32F205xx STM32F207xx ...

Page 2

Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

STM32F205xx, STM32F207xx 2.2.29 2.2.30 2.2.31 2.2.32 2.2.33 2.2.34 2.2.35 2.2.36 2.2.37 2.2.38 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

Contents 5.3.12 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 5.3.19 5.3.20 5.3.21 5.3.22 5.3.23 5.3.24 5.3.25 5.3.26 5.3.27 5.3.28 6 Package characteristics . . . . . . . . . . . . . . . . . . . ...

Page 5

STM32F205xx, STM32F207xx List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

List of tables Table 47. Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table ...

Page 7

STM32F205xx, STM32F207xx List of figures Figure 1. Compatible board design between STM32F10xx and STM32F2xx for LQFP64 package ...

Page 8

List of figures Figure 37. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 9

STM32F205xx, STM32F207xx Figure 86. USB OTG FS (full speed) device-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 10

... Introduction 1 Introduction This datasheet provides the description of the STM32F205xx, and STM32F207xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the The STM32F205xx, and STM32F207xx datasheet should be read in conjunction with the STM32F20x/STM32F21x reference manual. They will be referred to as STM32F20x devices throughout the document ...

Page 11

STM32F205xx, STM32F207xx 2 Description The STM32F20x family is based on the high-performance ARM core operating at a frequency 120 MHz. The family incorporates high-speed embedded memories (Flash memory Mbyte 128 Kbytes of ...

Page 12

Table 2. STM32F205xx features and peripheral counts Peripherals Flash memory in Kbytes 128 System 64 (SRAM1+SRAM2) (48+16) (80+16) SRAM in Kbytes Backup FSMC memory controller Ethernet General-purpose Timers Advanced-control Basic Random number generator 2 SPI/( USART ...

Page 13

Table 3. STM32F207xx features and peripheral counts Peripherals Flash memory in Kbytes 256 System (SRAM1+SRAM2) SRAM in Kbytes Backup FSMC memory controller Ethernet General-purpose Timers Advanced-control Basic Random number generator 2 SPI/( USART UART Comm. interfaces ...

Page 14

Description 2.1 Full compatibility throughout the family The STM32F205xx and STM32F207xx constitute the STM32F20x family whose members are fully pin-to-pin, software and feature compatible, allowing the user to try different memory densities and peripherals for a greater degree of freedom ...

Page 15

STM32F205xx, STM32F207xx Figure 2. Compatible board design between STM32F10xx and STM32F2xx for LQFP100 package Ω Figure 3. Compatible board design between STM32F10xx and STM32F2xx for LQFP144 package Ω 1. RFU = reserved for future use. Doc ID 15818 Rev 8 ...

Page 16

Description Figure 4. Compatible board design between STM32F10xx and STM32F2xx for LQFP176 package Ω 1. RFU = reserved for future use. 16/170 Doc ID 15818 Rev 8 STM32F205xx, STM32F207xx ...

Page 17

STM32F205xx, STM32F207xx 2.2 Device overview Figure 5. STM32F20x block diagram 1. The timers connected to APB2 are clocked from TIMxCLK up to 120 MHz, while the timers connected to APB1 are clocked from TIMxCLK MHz. Doc ID ...

Page 18

Description ® 2.2.1 ARM Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, ...

Page 19

STM32F205xx, STM32F207xx 2.2.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used ...

Page 20

Description 2.2.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They share some centralized FIFOs for APB/AHB peripherals, support burst transfer ...

Page 21

STM32F205xx, STM32F207xx 2.2.10 Nested vectored interrupt controller (NVIC) The STM32F205xx and STM32F207xx embed a nested vectored interrupt controller able to manage 16 priority levels, and handle maskable interrupt channels plus the 16 interrupt lines of the Cortex™-M3. ...

Page 22

Description 2.2.13 Boot modes At startup, boot pins are used to select one out of three boot options: ● Boot from user Flash ● Boot from system memory ● Boot from embedded SRAM The boot loader is located in system ...

Page 23

STM32F205xx, STM32F207xx 2.2.16 Voltage regulator The regulator has five operating modes: ● Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down ● Regulator OFF – Regulator OFF/internal reset ON – Regulator OFF/internal reset OFF Regulator ...

Page 24

Description Otherwise, PA0 should be asserted low externally during POR until V 1.8 V (see In this mode, PA0 cannot be used as a GPIO pin since it allows to reset the part of the 1.2 V logic which is ...

Page 25

STM32F205xx, STM32F207xx Figure 8. Startup in regulator OFF: fast V - power-down reset risen before V 2.2.17 Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F20x devices includes: ● The real-time clock (RTC) ● 4 ...

Page 26

Description 2.2.18 Low-power modes The STM32F20x family supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Sleep mode In Sleep mode, only the CPU is stopped. All peripherals ...

Page 27

STM32F205xx, STM32F207xx 2.2.20 Timers and watchdogs The STM32F205xx and STM32F207xx devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 4 compares the features of ...

Page 28

Description If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0- 100%). The TIM1 and TIM8 counters can be frozen in debug ...

Page 29

STM32F205xx, STM32F207xx main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs free-running timer for application timeout management hardware- ...

Page 30

Description Table 5. USART feature comparison USART Standard Modem LIN name features (RTS/CTS) USART1 X X USART2 X X USART3 X X UART4 X - UART5 X - USART6 X X 2.2.23 Serial peripheral interface (SPI) The STM32F20x feature up ...

Page 31

STM32F205xx, STM32F207xx 2.2.25 SDIO An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer MHz in 8-bit mode, ...

Page 32

Description 2.2.27 Controller area network (CAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames ...

Page 33

STM32F205xx, STM32F207xx suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: ● Combined Rx and Tx FIFO size of 1024× 35 bits ...

Page 34

Description 2.2.33 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down peripheral alternate function. ...

Page 35

STM32F205xx, STM32F207xx 2.2.36 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 and 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is ...

Page 36

Pinouts and pin description 3 Pinouts and pin description Figure 9. STM32F20x LQFP64 pinout Figure 10. STM32F20x WLCSP64+2 ballout 1. Top view. 36/170 ...

Page 37

STM32F205xx, STM32F207xx Figure 11. STM32F20x LQFP100 pinout 1. RFU means “reserved for future use”. This pin can be tied left unconnected Doc ID 15818 Rev 8 Pinouts and pin description 37/170 ...

Page 38

Pinouts and pin description Figure 12. STM32F20x LQFP144 pinout 1. RFU means “reserved for future use”. This pin can be tied to V 38/170 ,V or left unconnected Doc ID 15818 Rev 8 STM32F205xx, STM32F207xx ...

Page 39

STM32F205xx, STM32F207xx Figure 13. STM32F20x LQFP176 pinout 1. RFU means “reserved for future use”. This pin can be tied left unconnected Doc ID 15818 Rev 8 Pinouts and pin description 39/170 ...

Page 40

Pinouts and pin description Figure 14. STM32F20x UFBGA176 ballout PE3 PE2 PE1 PE0 B PE4 PE5 PE6 PB9 C VBAT PI7 PI6 PI5 PC13- PI8- D PI9 PI4 TAMP1 TAMP2 PC14- E PF0 PI10 ...

Page 41

STM32F205xx, STM32F207xx Table 6. STM32F20x pin and ball definitions (continued) Pins - - - - PC14 OSC32_OUT - - - ...

Page 42

Pinouts and pin description Table 6. STM32F20x pin and ball definitions (continued) Pins ...

Page 43

STM32F205xx, STM32F207xx Table 6. STM32F20x pin and ball definitions (continued) Pins ...

Page 44

Pinouts and pin description Table 6. STM32F20x pin and ball definitions (continued) Pins ...

Page 45

STM32F205xx, STM32F207xx Table 6. STM32F20x pin and ball definitions (continued) Pins R12 R13 M10 N10 - - - - 83 ...

Page 46

Pinouts and pin description Table 6. STM32F20x pin and ball definitions (continued) Pins P13 R14 R15 - - P15 - - 56 ...

Page 47

STM32F205xx, STM32F207xx Table 6. STM32F20x pin and ball definitions (continued) Pins - - - 92 111 J14 - - - 93 112 H14 - - - 94 113 G12 - - - 95 114 H13 115 ...

Page 48

Pinouts and pin description Table 6. STM32F20x pin and ball definitions (continued) Pins 105 124 A15 106 125 F13 - B1 74 107 126 F12 108 127 G13 - - - ...

Page 49

STM32F205xx, STM32F207xx Table 6. STM32F20x pin and ball definitions (continued) Pins 113 141 A12 - - 81 114 142 B12 - - 82 115 143 C12 116 144 D12 - - 84 117 145 ...

Page 50

Pinouts and pin description Table 6. STM32F20x pin and ball definitions (continued) Pins - - - 129 157 130 158 131 159 132 160 ...

Page 51

... Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F20x and STM32F21x reference manual, available from the STMicroelectronics website: www.st.com. ...

Page 52

Table 7. Alternate function mapping AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 TIM2_CH1 PA0-WKUP TIM 5_CH1 TIM8_ETR TIM2_ETR PA1 TIM2_CH2 TIM5_CH2 PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 PA4 TIM2_CH1 PA5 TIM8_CH1N TIM2_ETR PA6 TIM1_BKIN ...

Page 53

Table 7. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 PB14 TIM1_CH2N TIM8_CH2N PB15 RTC_50Hz TIM1_CH3N TIM8_CH3N PC0 PC1 PC2 PC3 PC4 PC5 PC6 TIM3_CH1 TIM8_CH1 PC7 TIM3_CH2 TIM8_CH2 PC8 TIM3_CH3 TIM8_CH3 PC9 ...

Page 54

Table 7. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 PD14 TIM4_CH3 PD15 TIM4_CH4 PE0 TIM4_ETR PE1 PE2 TRACECLK PE3 TRACED0 PE4 TRACED1 PE5 TRACED2 TIM9_CH1 PE6 TRACED3 TIM9_CH2 PE7 TIM1_ETR PE8 TIM1_CH1N ...

Page 55

Table 7. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 PF15 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PG10 PG11 PG12 PG13 PG14 PG15 PH0 - OSC_IN PH1 - OSC_OUT ...

Page 56

Table 7. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 PH14 TIM8_CH2N PH15 TIM8_CH3N PI0 TIM5_CH4 PI1 PI2 TIM8_CH4 PI3 TIM8_ETR PI4 TIM8_BKIN PI5 TIM8_CH1 PI6 TIM8_CH2 PI7 TIM8_CH3 PI8 PI9 PI10 PI11 ...

Page 57

STM32F205xx, STM32F207xx 4 Memory mapping The memory map is shown in Figure 15. Doc ID 15818 Rev 8 Memory mapping 57/170 ...

Page 58

Memory mapping Figure 15. Memory map 58/170 Doc ID 15818 Rev 8 STM32F205xx, STM32F207xx ...

Page 59

STM32F205xx, STM32F207xx 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...

Page 60

Electrical characteristics 5.1.6 Power supply scheme Figure 18. Power supply scheme 1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate ...

Page 61

STM32F205xx, STM32F207xx 5.1.7 Current consumption measurement Figure 19. Current consumption measurement scheme 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 9: Current characteristics, and permanent damage to the device. These are stress ratings only and ...

Page 62

Electrical characteristics Table 9. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control pin ...

Page 63

STM32F205xx, STM32F207xx Table 11. General operating conditions (continued) Symbol Parameter V Internal core voltage to be supplied CAP1 externally in REGOFF mode V CAP2 Power dissipation suffix 105 °C for suffix 7 ...

Page 64

Electrical characteristics Table 12. Limitations depending on the operating power supply range Maximum Operating power ADC supply operation range frequency (f 24 MHz with Conversion time up to 2.7 V memory wait 2 Msps 30 ...

Page 65

STM32F205xx, STM32F207xx Figure 20. Number of wait states versus The supply voltage can drop to 1.65 V when the device operates in a reduced temperature range. 5.3.2 VCAP1/VCAP2 external ...

Page 66

Electrical characteristics 5.3.3 Operating conditions at power-up / power-down (regulator ON) Subject to general operating conditions for T Table 14. Operating conditions at power-up / power-down (regulator ON) Symbol VDD V DD 5.3.4 Operating conditions at power-up ...

Page 67

STM32F205xx, STM32F207xx 5.3.5 Embedded reset and power control block characteristics The parameters given in temperature and V Table 16. Embedded reset and power control block characteristics Symbol Programmable voltage V PVD detector level selection (2) V PVD hysteresis PVDhyst Power-on/power-down ...

Page 68

Electrical characteristics Table 16. Embedded reset and power control block characteristics (continued) Symbol Brownout level 1 V BOR1 threshold Brownout level 2 V BOR2 threshold Brownout level 3 V BOR3 threshold (2) V BOR hysteresis BORhyst (2)(3) T Reset temporization ...

Page 69

STM32F205xx, STM32F207xx Typical and maximum current consumption The MCU is placed under the following conditions: ● At startup, all I/O pins are configured as analog inputs by firmware. ● All peripherals are disabled except explicitly mentioned. ● ...

Page 70

Electrical characteristics Table 18. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM Symbol Parameter Supply current Run mode 1. Code and data processing running ...

Page 71

STM32F205xx, STM32F207xx Figure 22. Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals ON Figure 23. Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals OFF ...

Page 72

Electrical characteristics Figure 24. Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals ON Figure 25. Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART ...

Page 73

STM32F205xx, STM32F207xx Table 19. Typical and maximum current consumption in Sleep mode Symbol Parameter External clock all peripherals enabled Supply current Sleep mode External clock peripherals disabled 1. Based on characterization, tested in production ...

Page 74

Electrical characteristics Figure 26. Typical current consumption vs temperature in Sleep mode, peripherals ON Figure 27. Typical current consumption vs temperature in Sleep mode, peripherals OFF 74/170 Doc ID 15818 Rev 8 STM32F205xx, STM32F207xx ...

Page 75

STM32F205xx, STM32F207xx Table 20. Typical and maximum current consumptions in Stop mode Symbol Parameter Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed oscillator Supply current OFF (no independent watchdog) in Stop mode with main Flash in ...

Page 76

Electrical characteristics Table 21. Typical and maximum current consumptions in Standby mode Symbol Parameter Backup SRAM ON, RTC ON Supply current Backup SRAM OFF, RTC Standby DD_STBY Backup SRAM ON, RTC OFF mode Backup SRAM OFF, RTC ...

Page 77

STM32F205xx, STM32F207xx Table 23. Peripheral current consumption Peripheral AHB1 AHB2 AHB3 (1) Typical consumption at 25 °C GPIO A GPIO B GPIO C GPIO D GPIO E GPIO F GPIO G GPIO H GPIO I OTG_HS + ULPI CRC BKPSRAM ...

Page 78

Electrical characteristics Table 23. Peripheral current consumption (continued) Peripheral APB1 78/170 (1) Typical consumption at 25 °C TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 TIM12 TIM13 TIM14 USART2 USART3 UART4 UART5 I2C1 I2C2 I2C3 SPI2 SPI3 CAN1 CAN2 (2) DAC channel ...

Page 79

STM32F205xx, STM32F207xx Table 23. Peripheral current consumption (continued) Peripheral APB2 1. External clock is 25 MHz (HSE oscillator with 25 MHz crystal) and PLL is on. 2. EN1 bit is set in DAC_CR register. 3. EN2 bit is set in ...

Page 80

Electrical characteristics 5.3.8 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in external clock source, and under ambient temperature and supply voltage conditions summarized in Table Table 25. High-speed external user clock ...

Page 81

STM32F205xx, STM32F207xx Figure 29. High-speed external clock source AC timing diagram V HSEH 90% 10% V HSEL t r(HSE) External clock source Figure 30. Low-speed external clock source AC timing diagram V LSEH 90% 10% V LSEL t r(LSE) External ...

Page 82

Electrical characteristics Table 27. HSE 4-26 MHz oscillator characteristics Symbol f Oscillator frequency OSC_IN R Feedback resistor F Recommended load capacitance C versus equivalent serial resistance of the crystal (R i HSE driving current 2 g Oscillator transconductance m (4) ...

Page 83

STM32F205xx, STM32F207xx Table 28. LSE oscillator characteristics (f Symbol R Feedback resistor F Recommended load capacitance (2) C versus equivalent serial resistance of the crystal (R I LSE driving current 2 g Oscillator Transconductance m (4) t startup time SU(LSE) ...

Page 84

Electrical characteristics 5.3.9 Internal clock source characteristics The parameters given in ambient temperature and V High-speed internal (HSI) RC oscillator Table 29. HSI oscillator characteristics Symbol Parameter f Frequency HSI Accuracy of the HSI ACC HSI oscillator HSI oscillator (3) ...

Page 85

STM32F205xx, STM32F207xx Low-speed internal (LSI) RC oscillator Table 30. LSI oscillator characteristics Symbol (2) f Frequency LSI (3) t LSI oscillator startup time su(LSI) (3) I LSI oscillator power consumption DD(LSI –40 to ...

Page 86

Electrical characteristics Table 31. Main PLL characteristics (continued) Symbol Parameter t PLL lock time LOCK Cycle-to-cycle jitter Period Jitter (3) Jitter Main clock output (MCO) for RMII Ethernet Main clock output (MCO) for MII Ethernet Bit Time CAN jitter (4) ...

Page 87

STM32F205xx, STM32F207xx Table 32. PLLI2S (audio PLL) characteristics Symbol Parameter Master I2S clock jitter (4) Jitter WS I2S clock jitter PLLI2S power consumption on (5) I DD(PLLI2S PLLI2S power consumption on (5) I DDA(PLLI2S) V DDA 1. TBD ...

Page 88

Electrical characteristics 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 33. SSCG parameters constraint Symbol f Mod md MODEPER * INCSTEP 1. Guaranteed by design, not ...

Page 89

STM32F205xx, STM32F207xx Figure 35 and Figure 36 down spread modes, where PLL_OUT T is the modulation period. mode md is the modulation depth. Figure 35. PLL output clock waveforms in center spread mode Figure 36. PLL output ...

Page 90

Electrical characteristics Table 35. Flash memory programming Symbol t Word programming time prog t Sector (16 KB) erase time ERASE16KB t Sector (64 KB) erase time ERASE64KB t Sector (128 KB) erase time ERASE128KB t Mass erase time ME V ...

Page 91

STM32F205xx, STM32F207xx Table 36. Flash memory programming with V Symbol t Double word programming prog t Sector (16 KB) erase time ERASE16KB t Sector (64 KB) erase time ERASE64KB t Sector (128 KB) erase time ERASE128KB t Mass erase time ...

Page 92

Electrical characteristics A device reset allows normal operations to be resumed. The test results are given in defined in application note AN1709. Table 38. EMS characteristics Symbol Voltage limits to be applied on any I/O pin to V FESD induce ...

Page 93

STM32F205xx, STM32F207xx Table 39. EMI characteristics Symbol Parameter package, conforming to SAE J1752/3 EEMBC, code running with ART enabled S Peak level EMI = 3 package, conforming to SAE J1752/3 ...

Page 94

Electrical characteristics Table 41. Electrical sensitivities Symbol Parameter LU Static latch-up class 5.3.15 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below V above V (for standard, 3 V-capable I/O ...

Page 95

STM32F205xx, STM32F207xx 5.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in performed under the conditions summarized in compliant. Table 43. I/O static characteristics Symbol Parameter V Input low level voltage IL (2) TT I/O input ...

Page 96

Electrical characteristics All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, ...

Page 97

STM32F205xx, STM32F207xx Input/output AC characteristics The definition and values of input/output AC characteristics are given in Table 45, respectively. Unless otherwise specified, the parameters given in performed under the ambient temperature and V in Table 11. Table 45. I/O AC ...

Page 98

Electrical characteristics Table 45. I/O AC characteristics OSPEEDRy [1:0] bit Symbol (1) value F Maximum frequency max(IO)out 11 Output high to low level fall t f(IO)out time Output low to high level rise t r(IO)out time Pulse width of external ...

Page 99

STM32F205xx, STM32F207xx 5.3.17 NRST pin characteristics The NRST pin input driver uses CMOS technology connected to a permanent pull-up resistor, R (see PU Unless otherwise specified, the parameters given in performed under the ambient temperature and V in ...

Page 100

Electrical characteristics 5.3.18 TIM timer characteristics The parameters given in Refer to Section 5.3.16: I/O port characteristics function characteristics (output compare, input capture, external clock, PWM output). Table 47. Characteristics of TIMx connected to the APB1 domain Symbol t Timer ...

Page 101

STM32F205xx, STM32F207xx Table 48. Characteristics of TIMx connected to the APB2 domain Symbol t Timer resolution time res(TIM) Timer external clock f EXT frequency on CH1 to CH4 Res Timer resolution TIM 16-bit counter clock period t when internal clock ...

Page 102

Electrical characteristics 2 Table 49 characteristics Symbol t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time h(SDA) t r(SDA) SDA and SCL rise time t ...

Page 103

STM32F205xx, STM32F207xx 2 Figure 39 bus AC waveforms and measurement circuit 1. Measurement points are done at CMOS levels: 0.3V Table 50. SCL frequency ( External pull-up resistance For speeds around 200 ...

Page 104

Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in are derived from tests performed under the ambient temperature, f supply voltage conditions summarized in Refer to Section 5.3.16: I/O port characteristics function characteristics ...

Page 105

STM32F205xx, STM32F207xx Figure 40. SPI timing diagram - slave mode and CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT Figure ...

Page 106

Electrical characteristics Figure 42. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 1. Measurement points are done at CMOS levels: 0.3V 106/170 ...

Page 107

STM32F205xx, STM32F207xx 2 Table 52 characteristics Symbol clock frequency 1/t c(CK r(CK clock rise and fall time t f(CK) ( valid time v(WS) ( hold ...

Page 108

Electrical characteristics 2 Figure 43 slave timing diagram (Philips protocol) CPOL = 0 CPOL = 1 WS input SD transmit SD receive 1. Measurement points are done at CMOS levels: 0.3 × LSB transmit/receive of the ...

Page 109

STM32F205xx, STM32F207xx USB OTG FS characteristics The USB OTG interface is USB-IF certified (Full-Spee the USB OTG HS and USB OTG FS controllers. Table 53. USB OTG FS startup time Symbol (1) t STARTUP 1. Guaranteed by design, not tested ...

Page 110

Electrical characteristics Figure 45. USB OTG FS timings: definition of data signal rise and fall time Differen tial data lines V CRS Table 55. USB OTG FS electrical characteristics Symbol t Rise time r t Fall time ...

Page 111

STM32F205xx, STM32F207xx Figure 46. ULPI timing diagram Table 58. ULPI timing Control in (ULPI_DIR) setup time Control in (ULPI_NXT) setup time Control in (ULPI_DIR, ULPI_NXT) hold time Data in setup time Data in hold time Control out (ULPI_STP) setup time ...

Page 112

Electrical characteristics Figure 47. Ethernet SMI timing diagram ETH_MDC ETH_MDIO(O) ETH_MDIO(I) Table 60. Dynamics characteristics: Ethernet MAC signals for SMI Symbol t MDC cycle time (2.38 MHz, AHB = 60 MHz) MDC t MDIO write data valid time d(MDIO) t ...

Page 113

STM32F205xx, STM32F207xx Table 62 gives the list of Ethernet MAC signals for MII and corresponding timing diagram. Figure 49. Ethernet MII timing diagram MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER MII_TX_CLK MII_TX_EN MII_TXD[3:0] Table 62. Dynamics characteristics: Ethernet MAC signals for MII Symbol ...

Page 114

Electrical characteristics 5.3.20 12-bit ADC characteristics Unless otherwise specified, the parameters given in performed under the ambient temperature, f conditions summarized in Table 63. ADC characteristics Symbol Parameter V Power supply DDA V Positive reference voltage REF+ f ADC clock ...

Page 115

STM32F205xx, STM32F207xx Table 63. ADC characteristics Symbol Parameter Sampling rate ( MHz) ADC ADC V DC current (4) REF I VREF+ consumption in conversion mode ADC VDDA DC current (4) I DDA consumption in conversion ...

Page 116

Electrical characteristics a Table 64. ADC accuracy Symbol ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error 1. Better performance could be achieved in restricted V 2. Based on characterization, not ...

Page 117

STM32F205xx, STM32F207xx Figure 51. Typical connection diagram using the ADC R AIN (1) V AIN 1. Refer to Table represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the parasitic pad capacitance ...

Page 118

Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in depending on whether V ceramic (good quality). They should be placed them as close as possible to the chip. Figure 52. Power supply and reference ...

Page 119

STM32F205xx, STM32F207xx 5.3.21 DAC electrical characteristics Table 65. DAC characteristics Symbol Parameter V Analog supply voltage DDA V Reference supply voltage REF+ V Ground SSA (2) R Resistive load with buffer ON LOAD Impedance output with buffer ( ...

Page 120

Electrical characteristics Table 65. DAC characteristics (continued) Symbol Parameter Integral non linearity (difference between measured value at Code i (3) INL and the value at Code line drawn between Code 0 and last Code 1023) Offset error ...

Page 121

STM32F205xx, STM32F207xx Figure 54. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. ...

Page 122

Electrical characteristics 5.3.24 Embedded reference voltage The parameters given in temperature and V Table 68. Embedded internal reference voltage Symbol V Internal reference voltage REFINT ADC sampling time when (1) T reading the internal reference S_vrefint voltage Internal reference voltage ...

Page 123

STM32F205xx, STM32F207xx Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 69. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to ...

Page 124

Electrical characteristics Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:0] FSMC_NBL[1:0] FSMC_D[15:0] FSMC_NADV 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings Symbol t FSMC_NE ...

Page 125

STM32F205xx, STM32F207xx Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms FSMC_NE FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 71. Asynchronous multiplexed PSRAM/NOR read timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NOE low v(NOE_NE) t FSMC_NOE low ...

Page 126

Electrical characteristics Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 72. Asynchronous multiplexed PSRAM/NOR write timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NWE low v(NWE_NE) t FSMC_NWE low ...

Page 127

STM32F205xx, STM32F207xx Synchronous waveforms and timings Figure 59 through Table 76 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● BurstAccessMode = FSMC_BurstAccessMode_Enable; ● MemoryType = FSMC_MemoryType_CRAM; ● WriteBurst = FSMC_WriteBurst_Enable; ...

Page 128

Electrical characteristics Table 73. Synchronous multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x=0..2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x= 0…2) d(CLKL-NExH) t FSMC_CLK low to FSMC_NADV low d(CLKL-NADVL) t FSMC_CLK ...

Page 129

STM32F205xx, STM32F207xx Figure 60. Synchronous multiplexed PSRAM write timings Table 74. Synchronous multiplexed PSRAM write timings Symbol t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-ADIV d(CLKL-DATA ...

Page 130

Electrical characteristics Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings Table 75. Synchronous non-multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x=0..2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x= 0…2) d(CLKL-NExH) t FSMC_CLK ...

Page 131

STM32F205xx, STM32F207xx Figure 62. Synchronous non-multiplexed PSRAM write timings Table 76. Synchronous non-multiplexed PSRAM write timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x=0..2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x= 0…2) d(CLKL-NExH) t FSMC_CLK ...

Page 132

Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 63 through Table 78 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime ...

Page 133

STM32F205xx, STM32F207xx Figure 64. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NREG FSMC_NIOWR FSMC_NIORD t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[15:0] High t v(NCE4_1-A) t d(NREG-NCE4_1) t d(NIORD-NCE4_1) t w(NWE) MEMxHIZ =1 t v(NWE-D) Doc ID 15818 ...

Page 134

Electrical characteristics Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG FSMC_NWE t d(NCE4_1-NOE) FSMC_NOE (1) FSMC_D[15:0] 1. Only data bits 0...7 are read (bits 8...15 are disregarded). 134/170 t v(NCE4_1-A) High ...

Page 135

STM32F205xx, STM32F207xx Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[7:0](1) 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 67. PC Card/CompactFlash controller ...

Page 136

Electrical characteristics Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access Table 77. Switching characteristics for PC Card/CF read and write cycles in attribute/common space Symbol t FSMC_Ncex low to FSMC_Ay valid v(NCEx-A) t FSMC_NCEx high to FSMC_Ax ...

Page 137

STM32F205xx, STM32F207xx Table 78. Switching characteristics for PC Card/CF read and write cycles in I/O space Symbol t FSMC_NIOWR low width w(NIOWR) t FSMC_NIOWR low to FSMC_D[15:0] valid v(NIOWR-D) t FSMC_NIOWR high to FSMC_D[15:0] invalid h(NIOWR-D) t FSMC_NCE4_1 low to ...

Page 138

Electrical characteristics Figure 69. NAND controller waveforms for read access Figure 70. NAND controller waveforms for write access 138/170 Doc ID 15818 Rev 8 STM32F205xx, STM32F207xx ...

Page 139

STM32F205xx, STM32F207xx Figure 71. NAND controller waveforms for common memory read access Figure 72. NAND controller waveforms for common memory write access Table 79. Switching characteristics for NAND Flash read cycles Symbol t FSMC_NOE low width w(N0E) FSMC_D[15-0] valid data ...

Page 140

Electrical characteristics Table 80. Switching characteristics for NAND Flash write cycles Symbol t FSMC_NWE low width w(NWE) t FSMC_NWE low to FSMC_D[15-0] valid v(NWE-D) t FSMC_NWE high to FSMC_D[15-0] invalid h(NWE-D) t FSMC_D[15-0] valid before FSMC_NWE high d(D-NWE) t FSMC_ALE ...

Page 141

STM32F205xx, STM32F207xx Figure 74. SD default mode Table 82 MMC characteristics Symbol Clock frequency in data transfer f PP mode - SDIO_CK/f t Clock low time, f W(CKL) t Clock high time, f W(CKH) t Clock rise time ...

Page 142

Package characteristics 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status ...

Page 143

STM32F205xx, STM32F207xx Figure 75. LQFP64 – pin low-profile quad flat package outline Drawing is not to scale. 2. Dimensions are in millimeters. Table 84. LQFP64 – ...

Page 144

Package characteristics Figure 77. WLCSP64+2 - 0.400 mm pitch wafer level chip size package outline 1. Drawing is not to scale. Table 85. WLCSP64+2 - 0.400 mm pitch wafer level chip size package mechanical data Symbol Typ A 0.570 A1 ...

Page 145

STM32F205xx, STM32F207xx Figure 78. LQFP100 100-pin low-profile quad flat package outline 100 Pin identification e 1. Drawing is not to scale. 2. Dimensions are in millimeters. ...

Page 146

Package characteristics Figure 80. LQFP144 mm, 144-pin low-profile quad flat package outline Seating plane ccc 108 109 144 Pin 1 1 identification 1. Drawing is not to scale. ...

Page 147

STM32F205xx, STM32F207xx Figure 82. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, package outline C Seating plane Pin 1 identification 1. Drawing is not to scale. Table 88. LQFP176 - Low profile quad flat package ...

Page 148

Package characteristics Figure 83. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline Seating plane Drawing is not to scale. Table 89. UFBGA176+25 - ultra thin ...

Page 149

STM32F205xx, STM32F207xx 6.2 Thermal characteristics The maximum chip-junction temperature, T using the following equation: Where: max is the maximum ambient temperature in °C, ● Θ is the package junction-to-ambient thermal resistance, in °C/W, ● JA ● P max ...

Page 150

Part numbering 7 Part numbering Table 91. Ordering information scheme Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 205 = STM32F20x, connectivity, USB OTG FS/HS 207= STM32F20x, connectivity, USB OTG FS/HS, camera interface,, ...

Page 151

STM32F205xx, STM32F207xx Appendix A Application block diagrams A.1 Main applications versus package Table 92 gives examples of configurations for each package. Table 92. Main applications versus package for STM32F2xxx microcontrollers (2) 64 pins Config Config 1 2 OTG USB - ...

Page 152

Application block diagrams A.2 Application example with regulator OFF Figure 84. Regulator OFF/internal reset ON 1. This mode is available only on UFBGA176 and WLCSP64+2 packages. Figure 85. Regulator OFF/ internal reset OFF 1. This mode is available only on ...

Page 153

STM32F205xx, STM32F207xx A.3 USB OTG full speed (FS) interface solutions Figure 86. USB OTG FS (full speed) device-only connection 1. The same application can be developed using the OTG mode to achieve enhanced performance thanks to the ...

Page 154

Application block diagrams Figure 88. OTG FS (full speed) connection dual-role with internal PHY 1. External voltage regulator only needed when building The current limiter is required only if the application has to support a V switch ...

Page 155

STM32F205xx, STM32F207xx A.4 USB OTG high speed (HS) interface solutions Figure 89. OTG HS (high speed) device connection, host and dual-role in high-speed mode with external PHY possible to use MCO1 or MCO2 to save a crystal. ...

Page 156

Application block diagrams A.5 Complete audio player solutions Two solutions are offered, illustrated in Figure 90 shows storage media to audio DAC/amplifier streaming using a software Codec. This solution implements an audio crystal to provide audio class I clock (0.5% ...

Page 157

STM32F205xx, STM32F207xx Figure 92. Audio player solution using PLL, PLLI2S, USB and 1 crystal Figure 93. Audio PLL (PLLI2S) providing accurate I2S clock 1 MHz CLKIN /M M=1,2,3,..,64 N=192,194,..,432 PLLI2S 192 to 432 MHz PhaseC VCO /N /R R=2,3,4,5,6,7 Doc ...

Page 158

Application block diagrams Figure 94. Master clock (MCK) used to drive the external audio DAC I2S_CK /I2SD 2,3,4,..,129 1. I2S_SCK is the I2S serial clock to the external audio DAC (not to be confused with I2S_CK). Figure 95. Master clock ...

Page 159

STM32F205xx, STM32F207xx A.6 Ethernet interface solutions Figure 96. MII mode using a 25 MHz crystal 1. f must be greater than 25 MHz. HCLK 2. Pulse per second when using IEEE1588 PTP optional signal. Figure 97. RMII with a 50 ...

Page 160

Application block diagrams Figure 98. RMII with a 25 MHz crystal and PHY with PLL 1. f must be greater than 25 MHz. HCLK 2. The 25 MHz (PHY_CLK) must be derived directly from the HSE oscillator, before the PLL ...

Page 161

STM32F205xx, STM32F207xx 8 Revision history Table 93. Document revision history Date Revision 05-Jun-2009 09-Oct-2009 01-Feb-2010 13-Jul-2010 1 Initial release. Document status promoted from Target specification to Preliminary data. In Table 6: STM32F20x pin and ball – Note 4 updated 2 ...

Page 162

Revision history Table 93. Document revision history (continued) Date Revision 13-Jul-2010 (continued) 162/170 Added USB OTG_FS features in on-the-go full-speed (OTG_FS). Updated V and V CAP_1 CAP_2 Power supply scheme. Removed DAC, modified ADC limitations, and updated I/O compensation for ...

Page 163

STM32F205xx, STM32F207xx Table 93. Document revision history (continued) Date Revision 25-Nov-2010 Update I/Os in Section : Features. Added WLCSP66(64+2) package. Added note 1 related to LQFP176 on cover page. ART accelerator. Added trademark for Adaptive real-time memory accelerator (ART Updated ...

Page 164

Revision history Table 93. Document revision history (continued) Date Revision 22-Apr-2011 164/170 Changed datasheet status to “Full Datasheet”. Introduced concept of SRAM1 and SRAM2. LQFP176 package now in production and offered only for 256 Kbyte and 1 Mbyte devices. Availability ...

Page 165

STM32F205xx, STM32F207xx Table 93. Document revision history (continued) Date Revision 22-Apr-2011 (continued) Updated Typical and maximum current consumption well as Table 17: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator ...

Page 166

Revision history Table 93. Document revision history (continued) Date Revision 22-Apr-2011 (continued) 166/170 Changed w(SCKH) w(SCLH Table 49: I f(SCK) f(SCL) bus AC waveforms and measurement Added Table 54: USB OTG FS DC ...

Page 167

STM32F205xx, STM32F207xx Table 93. Document revision history (continued) Date Revision 14-Jun-2011 Added SDIO in Table 2: STM32F205xx features and peripheral Updated V for 5V tolerant pins in IN Updated jitter parameters description in characteristics. Remove jitter values for system clock ...

Page 168

Revision history Table 93. Document revision history (continued) Date Revision 20-Dec-2011 168/170 Updated SDIO register addresses in Updated Figure 3: Compatible board design between STM32F10xx and STM32F2xx for LQFP144 design between STM32F10xx and STM32F2xx for LQFP100 Figure 1: Compatible board ...

Page 169

STM32F205xx, STM32F207xx Table 93. Document revision history (continued) Date Revision 20-Dec-2011 (continued) Appendix A.3: USB OTG full speed (FS) interface Figure 87: USB OTG FS (full speed) host-only connection Note 2 , updated Figure 88: OTG FS (full speed) connection ...

Page 170

... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

Related keywords