STM32F205ZG STMicroelectronics, STM32F205ZG Datasheet - Page 24

• Manufacturer Part Number: STM32F205ZG
• Description: High-performance ARM Cortex-M3 MCU with 1 Mbyte Flash, 120 MHz CPU, ART Accelerator
• Manufacturer: STMicroelectronics

Specifications of STM32F205ZG

• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII

Description
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Figure 7.
1. This figure is valid both whatever the internal reset mode (ON or OFF).
In this mode, PA0 cannot be used as a GPIO pin since it allows to reset the part of the
1.2 V logic which is not reset by the NRST pin, when the internal voltage regulator in
OFF.
Regulator OFF/internal reset OFF
On WLCSP66 package, this mode activated by connecting REGOFF to V
IRROFF to V
is available only on the WLCSP package. It allows to supply externally a 1.2 V voltage
source through V
The following conditions must be respected:
–
–
–
Otherwise, PA0 should be asserted low externally during POR until V
1.8 V (see
V
between power domains (see
PA0 should be kept low to cover both conditions: until V
1.08 V, and until V
NRST should be controlled by an external reset controller to keep the device
under reset when V
DD
Startup in regulator OFF: slow V
- power-down reset risen after V
should always be higher than V
DD
. IRROFF cannot be activated in conjunction with REGOFF. This mode
Figure
CAP_1
8).
DD
and V
DD
Doc ID 15818 Rev 8
reaches 1.65 V.
is below 1.65 V (see
CAP_2
Figure
pins, in addition to V
CAP_1
7).
CAP_1
DD
slope
and V
/V
Figure
CAP_2
CAP_2
STM32F205xx, STM32F207xx
8).
DD
stabilization
.
to avoid current injection
CAP_1
and V
CAP_2
SS
DD
and
reaches
reach