STM32F205ZG STMicroelectronics, STM32F205ZG Datasheet - Page 95
STM32F205ZG
Manufacturer Part Number
STM32F205ZG
Description
High-performance ARM Cortex-M3 MCU with 1 Mbyte Flash, 120 MHz CPU, ART Accelerator
Manufacturer
STMicroelectronics
Datasheet
1.STM32F205VE.pdf
(170 pages)
Specifications of STM32F205ZG
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
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STM32F205xx, STM32F207xx
5.3.16
Table 43.
1. If V
2. TT = 3.6 V tolerant.
3. FT = 5 V tolerant.
4. With a minimum of 100 mV.
5. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
6. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.
7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
8. Guaranteed by design, not tested in production.
Symbol
C
V
V
V
R
R
V
V
I
MOS/NMOS contribution
IH
IH
IO
lkg
hys
PU
PD
IL
IL
(1)
(1)
(8)
IH
maximum value cannot be respected, the injection current must be limited externally to I
Input low level voltage
TT
FT
Input low level voltage
TT I/O input high level voltage
FT I/O input high level voltage
I/O Schmitt trigger voltage hysteresis
IO FT Schmitt trigger voltage
hysteresis
I/O input leakage current
I/O FT input leakage current
Weak pull-up equivalent
resistor
Weak pull-down
equivalent resistor
I/O pin capacitance
(2)
(3)
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in
performed under the conditions summarized in
compliant.
I/O static characteristics
I/O input high level voltage
I/O input high level voltage
(7)
(5)
Parameter
to the series resistance is minimum
(6)
All pins
except for
PA10 and
PB12
PA10 and
PB12
All pins
except for
PA10 and
PB12
PA10 and
PB12
(6)
(5)
Doc ID 15818 Rev 8
2.7 V
1.8 V
2.0 V
(~10% order)
V
CMOS ports
CMOS ports
SS
Conditions
TTL ports
V
V
V
≤
≤
≤
≤
IN
IN
IN
V
V
V
V
=
=
DD
DD
DD
=
IN
V
V
5 V
≤
SS
DD
≤
≤
≤
.
V
Table
3.6 V
3.6 V
3.6 V
DD
Table 43
11. All I/Os are CMOS and TTL
5% V
V
V
0.7V
SS
SS
Min
2.0
2.0
30
30
8
8
-
-
-
–0.3
–0.3
DD
DD
are derived from tests
(4)
Electrical characteristics
INJ(PIN)
Typ
200
40
11
40
11
5
-
-
-
-
-
-
-
-
-
-
maximum value.
V
0.3V
DD
3.6
5.2
5.5
Max
0.8
5.5
±1
50
15
50
15
3
-
-
+0.3
(4)
(4)
(4)
DD
95/170
Unit
mV
µA
kΩ
pF
V