STM32F205ZG STMicroelectronics, STM32F205ZG Datasheet - Page 162

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STM32F205ZG

Manufacturer Part Number
STM32F205ZG
Description
High-performance ARM Cortex-M3 MCU with 1 Mbyte Flash, 120 MHz CPU, ART Accelerator
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F205ZG

10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII

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Revision history
162/170
Table 93.
13-Jul-2010
Date
Document revision history (continued)
(continued)
Revision
4
Added USB OTG_FS features in
on-the-go full-speed
Updated V
Power supply
Removed DAC, modified ADC limitations, and updated I/O
compensation for 1.8 to 2.1 V range in
on the operating power supply
Added V
and power control block
Removed table Typical current consumption in Sleep mode with Flash
memory in Deep power down mode. Merged typical and maximum
current consumption sections and added
maximum current consumption in Run mode, code with data
processing running from Flash memory (ART accelerator
Table 18: Typical and maximum current consumption in Run mode,
code with data processing running from Flash memory (ART
accelerator enabled) or RAM, Table 19: Typical and maximum current
consumption in Sleep mode, Table 20: Typical and maximum current
consumptions in Stop mode, Table 21: Typical and maximum current
consumptions in Standby
current consumptions in V
Update
PLL spread spectrum clock generation (SSCG)
Added
Updated
Added T
Updated
Removed 8-bit data in and data out waveforms from
timing
Removed note related to ADC calibration in
12-bit ADC
single table; tables ADC conversion time and ADC accuracy removed.
Updated
Updated
Section 5.3.23: V
Update
Added
characteristics, and
Added
LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm package
mechanical data
package 24 × 24 × 1.4 mm, package
Changed tape and reel code to TX in
scheme.
Added
microcontrollers. Updated figures in Appendix
speed (FS) interface solutions
interface
PLL, PLLI2S, USB and 1 crystal
providing accurate I2S
Doc ID 15818 Rev 8
diagram.
Note 8
Section 5.3.27: SD/SDIO MMC card host interface (SDIO)
Section 6.2: Thermal
Table 92: Main applications versus package for STM32F2xxx
Table 31: Main PLL characteristics
Section 5.3.26: Camera interface (DCMI) timing
NRST_OUT
BORL
Section 5.3.18: TIM timer
Table 49: I
Table 65: DAC
Section 5.3.22: Temperature sensor characteristics
solutions. Updated
CAP_1
characteristics: ADC characteristics tables merged into one
, V
scheme.
for CIO in
BORM
and V
and
BAT
in
2
Section 5.3.28: RTC
C
(OTG_FS).
monitoring
Table 46: NRST pin
Figure 82: LQFP176 - Low profile quad flat
, V
characteristics.
CAP_2
clock.
characteristics.
characteristics.
BORH
Table 43: I/O static
mode, and
BAT
characteristics. Updated
Figure 92: Audio player solution using
capacitor value to 2.2 µF in
mode.
and I
Changes
and
range.
characteristics.
and
Section 2.2.28: Universal serial bus
characteristics.
A.4: USB OTG high speed (HS)
RUSH
STM32F205xx, STM32F207xx
Table 22: Typical and maximum
Figure 93: Audio PLL (PLLI2S)
outline.
Table 91: Ordering information
Table 12: Limitations depending
in
characteristics.
Table 17: Typical and
characteristics.
and added
Table 16: Embedded reset
characteristics.
Table
A.3: USB OTG full
characteristics.
64.
Figure 46: ULPI
Table 88:
Section 5.3.20:
Section 5.3.11:
specifications.
Figure 18:
disabled),
and

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