STM32F205ZG STMicroelectronics, STM32F205ZG Datasheet - Page 168

• Manufacturer Part Number: STM32F205ZG
• Description: High-performance ARM Cortex-M3 MCU with 1 Mbyte Flash, 120 MHz CPU, ART Accelerator
• Manufacturer: STMicroelectronics

Specifications of STM32F205ZG

• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII

Revision history
168/170
Table 93.
20-Dec-2011
Date
Document revision history (continued)
Revision
8
Updated SDIO register addresses in
Updated
and STM32F2xx for LQFP144
design between STM32F10xx and STM32F2xx for LQFP100
Figure 1: Compatible board design between STM32F10xx and
STM32F2xx for LQFP64
board design between STM32F10xx and STM32F2xx for LQFP176
package.
Updated
Updated
Updated
(OTG_FS)
In
and SPI3_MCK to I2S2_MCK and I2S3_MCK, respectively. Added
ETH _RMII_TX_EN atlternate function to PG11. Added EVENTOUT in
the list of alternate functions for I/O pin/balls. Removed
OTG_FS_SDA, OTG_FS_SCL and OTG_FS_INTN alternate
functions.
In
I2S3_MCK for PC7/AF6, added FSMC_NCE3 for PG9, FSMC_NE3
for PG10, and FSMC_NCE2 for PD7. Removed OTG_FS_SDA,
OTG_FS_SCL and OTG_FS_INTN alternate functions. Changed
I2S3_SCK into I2S3_MCK for PC7/AF6. Updated peripherals
corresponding to AF12.
Removed CEXT and ESR from
conditions.
Added maximum power consumption at T
and maximum current consumptions in Stop
Updated md minimum value in
Added examples in
generation (SSCG)
Updated
characteristics.
Updated
Updated
SMI,
RMII, and
for
Section 5.3.25: FSMC
changed C
asynchronous timings and waveforms. Updated
Synchronous multiplexed PSRAM write
UpdatedTable 81: DCMI
Updated
10 × 10 × 0.6 mm mechanical
Updated
Table 6: STM32F20x pin and ball
Table 7: Alternate function
MII.
Doc ID 15818 Rev 8
Table 61: Dynamics characteristics: Ethernet MAC signals for
Table 60: Dynamics characteristics: Ethernet MAC signals for
Figure 3: Compatible board design between STM32F10xx
Section 2.2.3: Memory protection
Section 2.2.6: Embedded
Section 2.2.28: Universal serial bus on-the-go full-speed
Table 51: SPI characteristics
Figure 46: ULPI timing diagram
Table 89: UFBGA176+25 - ultra thin fine pitch ball grid array
Table 91: Ordering information
Table 62: Dynamics characteristics: Ethernet MAC signals
L
to remove external FS OTG PHY support.
value to 30 pF, and modified FSMC configuration for
Section 5.3.11: PLL spread spectrum clock
characteristics.
characteristics: updated
characteristics.
package, and added
mapping: changed I2S3_SCK to
Changes
data.
package,
Table 33: SSCG parameters
Table 11: General operating
SRAM.
definitions: changed SPI2_MCK
STM32F205xx, STM32F207xx
Figure 15: Memory
and
timings.
scheme.
Figure 2: Compatible board
and
A
=25 °C in
Table 52: I
unit.
mode.
Table 58: ULPI
Figure 4: Compatible
Table 69 toTable
Figure 60:
Table 20: Typical
2
S
map.
constraint.
package,
timing.
80,