STM32F205ZG STMicroelectronics, STM32F205ZG Datasheet - Page 166

• Manufacturer Part Number: STM32F205ZG
• Description: High-performance ARM Cortex-M3 MCU with 1 Mbyte Flash, 120 MHz CPU, ART Accelerator
• Manufacturer: STMicroelectronics

Specifications of STM32F205ZG

• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII

Revision history
166/170
Table 93.
22-Apr-2011
Date
Document revision history (continued)
(continued)
Revision
6
Changed t
t
bus AC waveforms and measurement
Added
updated
Updated V
characteristics.
Updated
Updated R
Updated t
Updated R typical value in
Updated
Modified FSMC_NOE waveform in
multiplexed SRAM/PSRAM/NOR read
FSMC_NEx/NADV/addresses/NWE/NOE/NWAIT of a half FSMC_CLK
period, changed t
AIV)
NWEH)
Synchronous multiplexed NOR/PSRAM read
Synchronous multiplexed PSRAM write
Synchronous non-multiplexed NOR/PSRAM read
Figure 62: Synchronous non-multiplexed PSRAM write
Changed t
t
modified t
Table
Updated note 2 in
Table
Modified t
waveforms for I/O space write
Modified FSMC_NCEx signal in
waveforms for read
write
memory read
common memory write access
Specified Full speed (FS) mode for
peripheral-only connection in FS mode
host-only connection in FS
f(SCK)
d(CLKH-NOEH)
, t
Doc ID 15818 Rev 8
d(CLKH-NOEH)
access,
76.
74,
, and updated data latency from 1 to 0 in
to t
Table 54: USB OTG FS DC electrical characteristics
Table 55: USB OTG FS electrical
Table 63: ADC characteristics
Table 68: Embedded internal reference
Table
f(SCL)
START
w(CLK)
h(NIOWR-D)
w(SCKH)
d(CLKH-NExH
DD
AIN
Figure 71: NAND controller waveforms for common
minimum value in
access, and
to t
equation. Updated
in
75, and
in
minimum value in
d(CLKL-NOEH)
d(CLKH-NExH
Table 49: I
Table 66: TS
to t
Table
to t
access,
in
w(SCLH)
d(CLKL-NOEH)
) to t
Figure 68: PC Card/CompactFlash controller
Table
69,
d(CLKL-NExH)
Figure 72: NAND controller waveforms for
Table 67: V
mode.
Figure 70: NAND controller waveforms for
Table
2
, t
) to t
C characteristics
, t
76.
Changes
access.
w(SCKL)
characteristics.
d(CLKH-NWEH)
Table 59: Ethernet DC electrical
Figure 69: NAND controller
Table 65: DAC
d(CLKL-NExH)
70,
Table
, and t
Figure 55: Asynchronous non-
Figure 89: USB OTG HS
STM32F205xx, STM32F207xx
Table
BAT
circuit.
to t
waveforms. Shifted end of
, t
and R
and
timings,
73,
d(CLKH-AIV)
d(CLKH-NWEH)
w(SCLL)
monitoring
characteristics.
Figure 90: USB OTG HS
71,
Table
timings,
AIN
to t
, t
and in
Figure 59:
d(CLKH-AIV)
Table
Figure 61:
characteristics.
, t
d(CLKL-NWEH)
voltage.
equation.
timings, and
74,
r(SCK)
to t
characteristics.
Figure 39: I
Figure 60:
72,
Table
to t
d(CLKL-AIV)
timings,
to t
Table
d(CLKL-
to t
r(SCL)
and
75, and
, and
d(CLKL-
73,
, and
2
,
C