ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 108

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
11.3.6
Table 49.
1. See note 4 in
2. See note 5 in
3. See note 4 in
11.3.7
108/247
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One-pulse mode
PWM mode
Modes
Summary of timer modes
Timer modes
Register description
Each timer is associated with three control and status registers, and with six pairs of data
registers (16-bit values) relating to the two input captures, the two output compares, the
counter and the alternate counter.
Control register 1 (CR1)
Read/Write
Reset value: 0000 0000 (00h)
Bit 7 = ICIE Input Capture Interrupt Enable.
Bit 6 = OCIE Output Compare Interrupt Enable.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
Bit 4 = FOLV2 Forced Output Compare 2.
One-pulse mode on page 103
One-pulse mode on page 103
: Pulse-width modulation mode on page 105
ICIE
7
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is
set.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even
if there is no successful comparison.
OCIE
Input Capture 1
TOIE
Yes
Yes
No
No
Doc ID 12321 Rev 5
FOLV2
Not recommended
Not recommended
Input Capture 2
Yes
Yes
Read/Write
Available resources
FOLV1
(1)
(3)
Output Compare 1 Output Compare 2
OLVL2
Yes
Yes
No
No
ST72344xx ST72345xx
IEDG1
Partially
Yes
Yes
No
OLVL1
(2)
0