ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 136

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
Note:
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Overrun error
Noise error
If the application Start Bit is not long enough to match the above requirements, then the NF
Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the
application software when the first valid byte is received.
An overrun error occurs when a character is received when RDRF has not been reset.
Data cannot be transferred from the shift register to the RDR register until the RDRF bit
is cleared.
When a overrun error occurs:
–
–
–
–
The OR bit is reset by an access to the SCISR register followed by a SCIDR register
read operation.
Oversampling techniques are used for data recovery by discriminating between valid
incoming data and noise.
Normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have
the same bit value, otherwise the NF flag is set. In the case of start bit detection, the NF
flag is set on the basis of an algorithm combining both valid edge detection and three
samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set during start bit
reception, there should be a valid edge detection as well as three valid samples.
When noise is detected in a frame:
–
–
–
The NF flag is reset by a SCISR register read operation followed by a SCIDR register
read operation.
During reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are
011,101,110), the frame is discarded and the receiving sequence is not started for this
frame. There is no RDRF bit set for this frame and the NF flag is set internally (not
accessible to the user). This NF flag is accessible along with the RDRF bit when a next
valid frame is received.
See also
The OR bit is set.
The RDR content is not lost.
The shift register is overwritten.
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR
register.
The NF flag is set at the rising edge of the RDRF bit.
Data is transferred from the Shift register to the SCIDR register.
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
Noise error
causes.
Doc ID 12321 Rev 5
ST72344xx ST72345xx