ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 69

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
Note:
Note:
1
2
3
4
As soon as active halt is enabled, executing a HALT instruction while the Watchdog is active
does not generate a reset. This means that the device cannot spend more than a defined
delay in this power saving mode.
Figure 30. Active-halt timing overview
Figure 31. Active-halt mode flowchart
This delay occurs only if the MCU exits Active-Halt mode by means of a reset.
Peripheral clocked with an external clock source can still be active.
Only the RTC interrupt and some specific interrupts can exit the MCU from Active-halt mode
(such as external interrupt). Refer to
Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits in the
CC register are set to the current software priority level of the interrupt routine and restored
when the CC register is popped.
(Active-halt enabled)
Run
instruction
HALT
(AWUCSR.AWUEN=0)
HALT INSTRUCTION
N
(MCCSR.OIE=1)
Active-
Doc ID 12321 Rev 5
halt
INTERRUPT
Y
Table 17 on page 59
256 OR 4096 cycle
delay (after reset)
3)
interrupt
256 OR 4096 CPU CLOCK
Reset
OR SERVICE INTERRUPT
FETCH RESET VECTOR
or
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
N
CYCLE DELAY
RESET
Y
for more details.
2)
XX
XX
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
10
4)
4)
vector
Fetch
Run
Power-saving modes
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