ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 144

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
Note:
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Control register 1 (SCICR1)
Reset value: x000 0000 (x0h)
Bit 7 = R8 Receive data bit 8.
Bit 6 = T8 Transmit data bit 8.
Bit 5 = SCID Disabled for low power consumption
Bit 4 = M Word length.
The M bit must not be modified during a data transfer (both transmission and reception).
Bit 3 = WAKE Wakeup method.
Bit 2 = PCE Parity control enable.
Bit 1 = PS Parity selection.
R8
This bit is used to store the 9th bit of the received word when M = 1.
This bit is used to store the 9th bit of the transmitted word when M = 1.
When this bit is set the SCI prescalers and outputs are stopped and the end of the
current byte transfer in order to reduce power consumption.This bit is set and cleared
by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
This bit determines the SCI Wake-Up method, it is set or cleared by software.
0: Idle Line
1: Address Mark
This bit selects the hardware parity control (generation and detection). When the parity
control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1;
8th bit if M = 0) and parity is checked on the received data. This bit is set and cleared
by software. Once it is set, PCE is active after the current byte (in reception and in
transmission).
0: Parity control disabled
1: Parity control enabled
This bit selects the odd or even parity when the parity generation/detection is enabled
(PCE bit set). It is set and cleared by software. The parity is selected after the current
byte.
0: Even parity
1: Odd parity
7
T8
SCID
Doc ID 12321 Rev 5
M
Read/Write
WAKE
PCE
ST72344xx ST72345xx
PS
PIE
0