ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 187

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
11.8.4
Note:
11.8.5
11.8.6
Changing the conversion channel
The application can change channels during conversion. When software modifies the
CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
Low-power modes
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed.
Table 72.
Interrupts
None.
Register description
Control/status register (ADCCSR)
Reset value: 0000 0000 (00h)
Bit 7 = EOC End of Conversion
Bit 6 = SPEED ADC clock selection
Bit 5 = ADON A/D Converter on
Bit 4 = Reserved. Must be kept cleared.
Wait
Halt
EOC
This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH
register or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
This bit is set and cleared by software.
0: f
1: f
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
7
Mode
ADC
ADC
= f
= f
Mode description
SPEED
CPU
CPU
/4
/2
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Converter requires a stabilization time
t
performed.
STAB
(see Electrical characteristics) before accurate conversions can be
ADON
Read/Write (Except bit 7 read only)
Doc ID 12321 Rev 5
0
Description
CH3
CH2
On-chip peripherals
CH1
CH0
187/247
0