ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 156
ST72344S4
Manufacturer Part Number
ST72344S4
Description
8-bit MCU
Manufacturer
STMicroelectronics
Datasheet
1.ST72344S4.pdf
(247 pages)
Specifications of ST72344S4
Up To 16 Kbytes Program Memory
single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55 °C.
Clock Sources
crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
5 Power-saving Modes
Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
16-bit Timer A With
1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
16-bit Timer B With
2 input captures, 2 output compares, PWM and pulse generator modes
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In all these cases, the SCL line is not held low; however, the SDA line can remain low if the
last bits transmitted are all 0. It is then necessary to release both lines by software. The SCL
line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.
master mode transmission. The resetting of the BUSY bit can then be handled in a
similar manner as the BERR flag being set.
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by
hardware with an interrupt if the ITE bit is set. To resume, set the Start or Stop bit.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and
the interface goes automatically back to slave mode (the M/SL bit is cleared).
Doc ID 12321 Rev 5
ST72344xx ST72345xx
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