ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 172

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
11.7.5
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Figure 74. 16-bit word read operation flowchart
Application note
Taking full advantage of its higher interrupt priority Slave 3 can be used to allow the
addressing master to send data bytes as commands to the ST7. These commands can be
decoded by the ST7 software to perform various operations such as programming the Data
E2PROM via IAP (In-Application Programming).
Slave 3 writes the command byte and other data in the RAM and generates an interrupt.
The ST7 then decodes the command and processes the data as decoded from the
command byte. The ST7 also writes a status byte in the RAM which the addressing master
can poll.
Address handling
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register. Then it is compared with the three addresses of the interface to decode
which slave of the interface is being addressed.
Address not matched: the interface ignores it and waits for another Start condition.
Repeat
Byte-Pair Coherency ensured by setting Word Mode + DMA on Words
RAM start address depends on slave address
Sends read address
Stop condition
Sends address
Receives byte 1
Receives byte 2
and read bit
Host
Updates status + DMA CNTL
Decodes I2C3SNS address
Updates current address-
Shadow reg => Shift reg
Reads 1 word from RAM
Byte 2 => Shadow reg
completes word write
Doc ID 12321 Rev 5
Byte 1 => Shift reg
Issues DMA request
Delays while CPU
Decodes R/W bit
Releases DMA
ST7 I2C3SNS
Resets read flag
Sets read flag
register
Word mode?
STOP?
N
Y
Y
N
Reads I2C3SNS status register
Services I2C3SNS interrupt
Resumes execution
Normal execution
Halts execution
ST7 CPU
ST72344xx ST72345xx
3 cycles
max