ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 90

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
11.2.7
Note:
90/247
Register description
MCC control/status register (MCCSR)
Reset value: 0000 0000 (00h)
Bit 7 = MCO Main clock out selection
To reduce power consumption, the MCO function is not active in Active-halt mode.
Bits 6:5 = CP[1:0] CPU clock prescaler
Table 41.
Bit 4 = SMS Slow mode select
Bits 3:2 = TB[1:0] Time base control
These bits select the programmable divider time base. They are set and cleared by
software.
MCO
This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by
software.
0: MCO alternate function disabled (I/O pin free for general-purpose I/O)
1: MCO alternate function enabled (f
These bits select the CPU clock prescaler which is applied in the different slow modes.
Their action is conditioned by the setting of the SMS bit. These two bits are set and
cleared by software.
This bit is set and cleared by software.
0: Normal mode. f
1: Slow mode. f
See
page 82
7
Section 9.2: Slow mode
CPU clock prescaler selection
for more details.
CP1
f
CPU
CPU
f
in Slow mode
f
f
f
OSC2
OSC2
OSC2
OSC2
CPU
is given by CP1, CP0
CP0
/ 16
=
/ 2
/ 4
/ 8
f
OSC2
Doc ID 12321 Rev 5
and
SMS
Section 11.1: Window watchdog (WWDG) on
Read/Write
CPU
on I/O port)
TB1
CP1
TB0
0
0
1
1
ST72344xx ST72345xx
OIE
CP0
0
1
0
1
OIF
0