ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 183

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
Note:
I2C slave 1 memory current address register (I2C3SCAR1)
Reset value: 0000 0000 (00h)
Bit 7:0 = CA[7:0] Current address of Slave 1 buffer
I2C slave 2 memory current address register (I2C3SCAR2)
Reset value: 0000 0000 (00h)
Bit 7:0 = CA[7:0] Current address of Slave 2 buffer
I2C slave 3 memory current address register (I2C3SCAR3)
Reset value: 0000 0000 (00h)
Bit 6:0 = CA[6:0] Current address of Slave 3 buffer
Slave address 3 can store only 128 bytes. For slave address 3, CA7 bit will remain 0. i.e. if
the Byte Address sent is 0x80 then the Current Address register will hold the value 0x00 due
to an overflow.
Table 71.
Address
(Hex.)
0060h
0061h
0062h
0063h
0064h
0065h
CA7
CA7
CA7
This register contains the 8 bit offset of Slave Address 1 reserved area in RAM. It is
also cleared by hardware when interface is disabled (PE =0).
This register contains the 8-bit offset of Slave Address 2 reserved area in RAM. It is
also cleared by hardware when interface is disabled (PE =0).
This register contains the 8-bit offset of slave address 3 reserved area in RAM. It is also
cleared by hardware when interface is disabled (PE =0).
7
7
7
I2C3SCAR1
I2C3SSAR1 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1
I2C3SBCR
I2C3SCR1
I2C3SCR2
I2C3SSR
Register
I
name
2
C3S register map
CA6
CA6
CA6
NACK
NB7
PL1
7
0
CA5
CA5
CA5
Doc ID 12321 Rev 5
BERR
NB6
PL0
6
0
CA4
CA4
CA4
WF3
Read only
Read only
Read only
NB5
5
0
0
CA3
CA3
CA3
ITER
WP2
WF2
NB4
4
CA 7 .. CA0
ITRE3 ITRE1/2 ITWE3 ITWE1/2
WP1
WF1
NB3
3
CA2
CA2
CA2
NB2
RF3
PE
2
On-chip peripherals
CA1
CA1
CA1
BusyW
RF2
NB1
1
CA0
CA0
CA0
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NB1
EN1
B/W
RF1
0
0
0
0