TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 177

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

TBnMOD
(0x4001_0xxC)
＜TBCLK1:0＞:Selects the TMRBn timer count clock.
＜TBCLE＞:Clears and controls the TMRBn up-counter.
9.4.1.4 TMRB mode register (channels 0 thorough 7)
Read/Write
After reset
Read/Write
Read/Write
Read/Write
bit Symbol
bit Symbol
bit Symbol
bit Symbol
After reset
After reset
After reset
Function
"00" is disable in case of using TMRB3 and TMRB5 of TMPM382.
“0”
is read.
31
23
15
00: select TBnIN input pin
01: select φT1
10: select φT4
11: select φT16 (1/32φT0)
“0”: Disables clearing of the up-counter.
“1”: Clears up-counter if there is a match with timer register 1 (TBnRG1).
R
R
R
7
R
0
0
0
0
Writes to
0 and 1
(when
1: Must be
timer
registers
double
buffering is
enabled)
written
separately
written
simultaneo
usly
TBRSWR
0: Can be
R/W
30
22
14
R
R
R
6
0
0
0
0
TMRBn mode register(n=0~7)
Software
capture
control
0: Software
capture
1: Don't
care
(1/8φT0)
TBCP
(1/2φT0)
29
21
13
W
TMPM380/M382 - 11 / 34 -
R
R
R
5
0
0
0
1
00: Disable
01: TBnIN↑
10: TBnIN↑ TBnIN↓
11: TBnOUT↑ TBnOUT↓
Capture timing
TBCPM1
28
20
12
R
R
R
4
0
0
0
0
TBCPM0
27
19
11
R
R
R
3
0
0
0
0
Up-counter
clear
control
0:Clear and
disable
1:Clear and
enable
TBCLE
R/W
26
18
10
R
R
R
2
0
0
0
0
00: TBnIN pin input
01: φT1
10: φT4
11: φT16
Source clock
TBCLK1
25
17
R
R
9
R
1
0
0
0
0
TMPM380/M382
TBCLK0
24
16
R
R
R
8
0
0
0
0
0